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radv: rework emitting inner coverage when a fragment shader is bound

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To stop relying on the pipeline. The state is now flagged when a new
fragment shader with a different inner coverage setting is bound.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22194>
This commit is contained in:
Samuel Pitoiset
2023-03-27 15:42:31 +02:00
committed by Marge Bot
parent 5231643900
commit bc39fa9500
3 changed files with 11 additions and 14 deletions
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18
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1872,9 +1872,6 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control ||
cmd_buffer->state.emitted_graphics_pipeline->rast_prim != pipeline->rast_prim)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
if (cmd_buffer->state.emitted_graphics_pipeline->uses_inner_coverage != pipeline->uses_inner_coverage)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE;
}
radeon_emit_array(cmd_buffer->cs, pipeline->base.cs.buf, pipeline->base.cs.cdw);
@@ -2474,7 +2471,6 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_conservative_rast_mode(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
@@ -2482,12 +2478,14 @@ radv_emit_conservative_rast_mode(struct radv_cmd_buffer *cmd_buffer)
uint32_t pa_sc_conservative_rast;
if (d->vk.rs.conservative_mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
/* Inner coverage requires underestimate conservative rasterization. */
if (d->vk.rs.conservative_mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT &&
!pipeline->uses_inner_coverage) {
!ps->info.ps.reads_fully_covered) {
pa_sc_conservative_rast |= S_028C4C_OVER_RAST_ENABLE(1) |
S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
@@ -4229,8 +4227,8 @@ lookup_ps_epilog(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer);
const struct radv_rendering_state *render = &cmd_buffer->state.render;
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
@@ -4289,7 +4287,7 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
S_028BE0_COVERED_CENTROID_IS_CENTER(pdevice->rad_info.gfx_level >= GFX10_3);
}
pa_sc_aa_config |= S_028BE0_COVERAGE_TO_SHADER_SELECT(pipeline->uses_inner_coverage);
pa_sc_aa_config |= S_028BE0_COVERAGE_TO_SHADER_SELECT(ps->info.ps.reads_fully_covered);
radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, db_eqaa);
radeon_set_context_reg(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, pa_sc_aa_config);
@@ -6366,6 +6364,8 @@ radv_bind_mesh_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shad
static void
radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *ps)
{
const struct radv_shader *previous_ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
if (ps->info.ps.needs_sample_positions) {
cmd_buffer->sample_positions_needed = true;
}
@@ -6375,6 +6375,10 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
}
/* Re-emit the conservative rasterization mode because inner coverage is different. */
if (previous_ps && previous_ps->info.ps.reads_fully_covered != ps->info.ps.reads_fully_covered)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE;
cmd_buffer->state.ms.sample_shading_enable = ps->info.ps.uses_sample_shading;
if (ps->info.ps.uses_sample_shading)
cmd_buffer->state.ms.min_sample_shading = 1.0f;

2
src/amd/vulkan/radv_pipeline.c
View File

@@ -4740,8 +4740,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.has_ngg_culling;
pipeline->force_vrs_per_vertex =
pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex;
pipeline->uses_inner_coverage =
pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.reads_fully_covered;
pipeline->rast_prim = vgt_gs_out_prim_type;
pipeline->base.push_constant_size = pipeline_layout.push_constant_size;

5
src/amd/vulkan/radv_private.h
View File

@@ -2205,11 +2205,6 @@ struct radv_graphics_pipeline {
bool uses_drawid;
bool uses_baseinstance;
/* Whether the pipeline uses inner coverage which means that a fragment has all of its pixel
* squares fully covered by the generating primitive.
*/
bool uses_inner_coverage;
bool need_null_export_workaround;
/* Whether the pipeline forces per-vertex VRS (GFX10.3+). */
bool force_vrs_per_vertex;