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ac/registers: allow to parse GCVM_L2_PROTECTION_FAULT_STATUS

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To have defined bitfields for this register.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25855>
This commit is contained in:
Samuel Pitoiset
2023-10-23 19:03:22 +02:00
committed by Marge Bot
parent 7d96fe853e
commit bc09932ec3
5 changed files with 84 additions and 0 deletions
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20
src/amd/registers/gfx10.json
View File

@@ -1756,6 +1756,12 @@
"name": "GB_MACROTILE_MODE15",
"type_ref": "GB_MACROTILE_MODE0"
},
{
"chips": ["gfx10"],
"map": {"at": 41264, "to": "mm"},
"name": "GCVM_L2_PROTECTION_FAULT_STATUS",
"type_ref": "GCVM_L2_PROTECTION_FAULT_STATUS"
},
{
"chips": ["gfx10"],
"map": {"at": 45060, "to": "mm"},
@@ -13017,6 +13023,20 @@
{"bits": [28, 31], "name": "CNTL_MODE"}
]
},
"GCVM_L2_PROTECTION_FAULT_STATUS": {
"fields": [
{"bits": [0, 0], "name": "MORE_FAULTS"},
{"bits": [1, 3], "name": "WALKER_ERROR"},
{"bits": [4, 7], "name": "PERMISSION_FAULTS"},
{"bits": [8, 8], "name": "MAPPING_ERROR"},
{"bits": [9, 17], "name": "CID"},
{"bits": [18, 18], "name": "RW"},
{"bits": [19, 19], "name": "ATOMIC"},
{"bits": [20, 23], "name": "VMID"},
{"bits": [24, 24], "name": "VF"},
{"bits": [25, 29], "name": "VFID"}
]
},
"GC_ATC_L2_PERFCOUNTER0_CFG": {
"fields": [
{"bits": [0, 7], "name": "PERF_SEL"},

20
src/amd/registers/gfx103.json
View File

@@ -1405,6 +1405,12 @@
"name": "GB_ADDR_CONFIG",
"type_ref": "GB_ADDR_CONFIG"
},
{
"chips": ["gfx103"],
"map": {"at": 41120, "to": "mm"},
"name": "GCVM_L2_PROTECTION_FAULT_STATUS",
"type_ref": "GCVM_L2_PROTECTION_FAULT_STATUS"
},
{
"chips": ["gfx103"],
"map": {"at": 45060, "to": "mm"},
@@ -12908,6 +12914,20 @@
{"bits": [28, 31], "name": "CNTL_MODE"}
]
},
"GCVM_L2_PROTECTION_FAULT_STATUS": {
"fields": [
{"bits": [0, 0], "name": "MORE_FAULTS"},
{"bits": [1, 3], "name": "WALKER_ERROR"},
{"bits": [4, 7], "name": "PERMISSION_FAULTS"},
{"bits": [8, 8], "name": "MAPPING_ERROR"},
{"bits": [9, 17], "name": "CID"},
{"bits": [18, 18], "name": "RW"},
{"bits": [19, 19], "name": "ATOMIC"},
{"bits": [20, 23], "name": "VMID"},
{"bits": [24, 24], "name": "VF"},
{"bits": [25, 29], "name": "VFID"}
]
},
"GDS_ATOM_BASE": {
"fields": [
{"bits": [0, 15], "name": "BASE"},

21
src/amd/registers/gfx11.json
View File

@@ -1293,6 +1293,12 @@
"name": "GB_ADDR_CONFIG",
"type_ref": "GB_ADDR_CONFIG"
},
{
"chips": ["gfx11"],
"map": {"at": 41120, "to": "mm"},
"name": "GCVM_L2_PROTECTION_FAULT_STATUS",
"type_ref": "GCVM_L2_PROTECTION_FAULT_STATUS"
},
{
"chips": ["gfx11"],
"map": {"at": 45060, "to": "mm"},
@@ -11731,6 +11737,21 @@
{"bits": [20, 23], "name": "COMPARE_VALUE3"}
]
},
"GCVM_L2_PROTECTION_FAULT_STATUS": {
"fields": [
{"bits": [0, 0], "name": "MORE_FAULTS"},
{"bits": [1, 3], "name": "WALKER_ERROR"},
{"bits": [4, 7], "name": "PERMISSION_FAULTS"},
{"bits": [8, 8], "name": "MAPPING_ERROR"},
{"bits": [9, 17], "name": "CID"},
{"bits": [18, 18], "name": "RW"},
{"bits": [19, 19], "name": "ATOMIC"},
{"bits": [20, 23], "name": "VMID"},
{"bits": [24, 24], "name": "VF"},
{"bits": [25, 28], "name": "VFID"},
{"bits": [29, 29], "name": "PRT"}
]
},
"GDS_ATOM_BASE": {
"fields": [
{"bits": [0, 11], "name": "BASE"},

22
src/amd/registers/gfx115.json
View File

@@ -1262,6 +1262,12 @@
"name": "GB_ADDR_CONFIG",
"type_ref": "GB_ADDR_CONFIG"
},
{
"chips": ["gfx115"],
"map": {"at": 41136, "to": "mm"},
"name": "GCVM_L2_PROTECTION_FAULT_STATUS",
"type_ref": "GCVM_L2_PROTECTION_FAULT_STATUS"
},
{
"chips": ["gfx115"],
"map": {"at": 45060, "to": "mm"},
@@ -11592,6 +11598,22 @@
{"bits": [20, 23], "name": "COMPARE_VALUE3"}
]
},
"GCVM_L2_PROTECTION_FAULT_STATUS": {
"fields": [
{"bits": [0, 0], "name": "MORE_FAULTS"},
{"bits": [1, 3], "name": "WALKER_ERROR"},
{"bits": [4, 7], "name": "PERMISSION_FAULTS"},
{"bits": [8, 8], "name": "MAPPING_ERROR"},
{"bits": [9, 17], "name": "CID"},
{"bits": [18, 18], "name": "RW"},
{"bits": [19, 19], "name": "ATOMIC"},
{"bits": [20, 23], "name": "VMID"},
{"bits": [24, 24], "name": "VF"},
{"bits": [25, 28], "name": "VFID"},
{"bits": [29, 29], "name": "PRT"},
{"bits": [30, 30], "name": "FED"}
]
},
"GC_ATC_L2_PERFCOUNTER2_SELECT": {
"fields": [
{"bits": [0, 9], "name": "PERF_SEL0"},

1
src/amd/registers/parse_kernel_headers.py
View File

@@ -106,6 +106,7 @@ def register_filter(gfx_level, name, offset, already_added):
name.startswith('SQ_THREAD') or
name.startswith('GRBM_STATUS') or
name.startswith('CP_CP'))) or
name.startswith('GCVM_L2_PROTECTION_FAULT_STATUS') or
# Add registers in the 0x9000 range
(group == 0x9 and
(name in ['TA_CS_BC_BASE_ADDR', 'GB_ADDR_CONFIG', 'SPI_CONFIG_CNTL'] or