diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index cdbe3a6dcf9..da7c09c96f2 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -477,14 +477,6 @@ enum opcode { SHADER_OPCODE_URB_WRITE_MASKED_LOGICAL, SHADER_OPCODE_URB_WRITE_MASKED_PER_SLOT_LOGICAL, - SHADER_OPCODE_URB_READ_SIMD8, - SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, - - SHADER_OPCODE_URB_WRITE_SIMD8, - SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT, - SHADER_OPCODE_URB_WRITE_SIMD8_MASKED, - SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT, - /** * Return the index of the first enabled live channel and assign it to * to the first component of the destination. Frequently used as input diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index b2cbe3bd65c..d139b1caa62 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -224,12 +224,6 @@ fs_inst::is_send_from_grf() const case FS_OPCODE_INTERPOLATE_AT_SAMPLE: case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: - case SHADER_OPCODE_URB_WRITE_SIMD8: - case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: - case SHADER_OPCODE_URB_READ_SIMD8: - case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: case SHADER_OPCODE_INTERLOCK: case SHADER_OPCODE_MEMORY_FENCE: case SHADER_OPCODE_BARRIER: @@ -299,12 +293,6 @@ fs_inst::is_payload(unsigned arg) const switch (opcode) { case FS_OPCODE_FB_WRITE: case FS_OPCODE_FB_READ: - case SHADER_OPCODE_URB_WRITE_SIMD8: - case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: - case SHADER_OPCODE_URB_READ_SIMD8: - case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: case VEC4_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_SURFACE_READ: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: @@ -903,12 +891,6 @@ fs_inst::size_read(int arg) const break; case FS_OPCODE_FB_READ: - case SHADER_OPCODE_URB_WRITE_SIMD8: - case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: - case SHADER_OPCODE_URB_READ_SIMD8: - case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: case SHADER_OPCODE_URB_WRITE_LOGICAL: case SHADER_OPCODE_URB_WRITE_PER_SLOT_LOGICAL: case SHADER_OPCODE_URB_WRITE_MASKED_LOGICAL: @@ -5083,12 +5065,6 @@ get_lowered_simd_width(const struct brw_compiler *compiler, case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: return 8; - case SHADER_OPCODE_URB_READ_SIMD8: - case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: - case SHADER_OPCODE_URB_WRITE_SIMD8: - case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: case SHADER_OPCODE_URB_READ_LOGICAL: case SHADER_OPCODE_URB_READ_PER_SLOT_LOGICAL: case SHADER_OPCODE_URB_WRITE_LOGICAL: diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 11f831fdbcd..8910776f924 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -784,61 +784,6 @@ fs_generator::generate_quad_swizzle(const fs_inst *inst, } } -void -fs_generator::generate_urb_read(fs_inst *inst, - struct brw_reg dst, - struct brw_reg header) -{ - assert(inst->size_written % REG_SIZE == 0); - assert(header.file == BRW_GENERAL_REGISTER_FILE); - assert(header.type == BRW_REGISTER_TYPE_UD); - - brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); - brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD)); - brw_set_src0(p, send, header); - if (devinfo->ver < 12) - brw_set_src1(p, send, brw_imm_ud(0u)); - - brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB); - brw_inst_set_urb_opcode(p->devinfo, send, GFX8_URB_OPCODE_SIMD8_READ); - - if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT) - brw_inst_set_urb_per_slot_offset(p->devinfo, send, true); - - brw_inst_set_mlen(p->devinfo, send, inst->mlen); - brw_inst_set_rlen(p->devinfo, send, inst->size_written / REG_SIZE); - brw_inst_set_header_present(p->devinfo, send, true); - brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset); -} - -void -fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload) -{ - brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND); - - brw_set_dest(p, insn, brw_null_reg()); - brw_set_src0(p, insn, payload); - if (devinfo->ver < 12) - brw_set_src1(p, insn, brw_imm_ud(0u)); - - brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB); - brw_inst_set_urb_opcode(p->devinfo, insn, GFX8_URB_OPCODE_SIMD8_WRITE); - - if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT || - inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) - brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true); - - if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED || - inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) - brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true); - - brw_inst_set_mlen(p->devinfo, insn, inst->mlen); - brw_inst_set_rlen(p->devinfo, insn, 0); - brw_inst_set_eot(p->devinfo, insn, inst->eot); - brw_inst_set_header_present(p->devinfo, insn, true); - brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset); -} - void fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload) { @@ -2319,20 +2264,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, brw_MOV_reloc_imm(p, dst, dst.type, src[0].ud); break; - case SHADER_OPCODE_URB_READ_SIMD8: - case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: - generate_urb_read(inst, dst, src[0]); - send_count++; - break; - - case SHADER_OPCODE_URB_WRITE_SIMD8: - case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: - generate_urb_write(inst, src[0]); - send_count++; - break; - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: assert(inst->force_writemask_all); generate_uniform_pull_constant_load(inst, dst, src[0], src[1]); diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp index f7292df7176..3548cef79ce 100644 --- a/src/intel/compiler/brw_ir_performance.cpp +++ b/src/intel/compiler/brw_ir_performance.cpp @@ -922,12 +922,6 @@ namespace { 8 /* XXX */, 750 /* XXX */, 0, 0, 2 /* XXX */, 0); - case SHADER_OPCODE_URB_READ_SIMD8: - case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: - case SHADER_OPCODE_URB_WRITE_SIMD8: - case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: case VEC4_OPCODE_URB_READ: case VEC4_VS_OPCODE_URB_WRITE: case VEC4_GS_OPCODE_URB_WRITE: diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 838097d6ddb..388712f0193 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -371,18 +371,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op) return "gfx7_scratch_read"; case SHADER_OPCODE_SCRATCH_HEADER: return "scratch_header"; - case SHADER_OPCODE_URB_WRITE_SIMD8: - return "gfx8_urb_write_simd8"; - case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: - return "gfx8_urb_write_simd8_per_slot"; - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: - return "gfx8_urb_write_simd8_masked"; - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: - return "gfx8_urb_write_simd8_masked_per_slot"; - case SHADER_OPCODE_URB_READ_SIMD8: - return "urb_read_simd8"; - case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: - return "urb_read_simd8_per_slot"; case SHADER_OPCODE_URB_WRITE_LOGICAL: return "urb_write_logical"; @@ -1148,10 +1136,6 @@ backend_instruction::has_side_effects() const case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_MEMORY_FENCE: case SHADER_OPCODE_INTERLOCK: - case SHADER_OPCODE_URB_WRITE_SIMD8: - case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: - case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: case SHADER_OPCODE_URB_WRITE_LOGICAL: case SHADER_OPCODE_URB_WRITE_PER_SLOT_LOGICAL: case SHADER_OPCODE_URB_WRITE_MASKED_LOGICAL: @@ -1191,8 +1175,6 @@ backend_instruction::is_volatile() const case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: - case SHADER_OPCODE_URB_READ_SIMD8: - case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: case VEC4_OPCODE_URB_READ: return true; default: