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nir,ac/llvm: add nir_buffer_atomic_add_amd

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Used by radeonsi for lower nir_atomic_add_gen/xfb_prim_count_amd.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
This commit is contained in:
Qiang Yu
2022-08-11 10:17:16 +08:00
committed by Marge Bot
parent 7cec2e7520
commit bb837bf6ef
3 changed files with 24 additions and 0 deletions
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20
src/amd/llvm/ac_nir_to_llvm.c
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@@ -4315,6 +4315,26 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
ac_build_atomic_rmw(&ctx->ac, LLVMAtomicRMWBinOpAdd, gds_base, store_val, "workgroup-one-as"); ac_build_atomic_rmw(&ctx->ac, LLVMAtomicRMWBinOpAdd, gds_base, store_val, "workgroup-one-as");
break; break;
} }
case nir_intrinsic_buffer_atomic_add_amd: {
LLVMValueRef desc = get_src(ctx, instr->src[0]);
LLVMValueRef data = get_src(ctx, instr->src[1]);
unsigned base = nir_intrinsic_base(instr);
LLVMTypeRef return_type = LLVMTypeOf(data);
LLVMValueRef args[] = {
data, desc,
LLVMConstInt(ctx->ac.i32, base, false),
ctx->ac.i32_0, /* soffset */
ctx->ac.i32_0, /* cachepolicy */
};
char name[64], type[8];
ac_build_type_name_for_intr(return_type, type, sizeof(type));
snprintf(name, sizeof(name), "llvm.amdgcn.raw.buffer.atomic.add.%s", type);
result = ac_build_intrinsic(&ctx->ac, name, return_type, args, 5, 0);
break;
}
case nir_intrinsic_export_vertex_amd: case nir_intrinsic_export_vertex_amd:
ctx->abi->export_vertex(ctx->abi); ctx->abi->export_vertex(ctx->abi);
break; break;

1
src/compiler/nir/nir_divergence_analysis.c
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@@ -652,6 +652,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_load_packed_passthrough_primitive_amd: case nir_intrinsic_load_packed_passthrough_primitive_amd:
case nir_intrinsic_load_initial_edgeflags_amd: case nir_intrinsic_load_initial_edgeflags_amd:
case nir_intrinsic_gds_atomic_add_amd: case nir_intrinsic_gds_atomic_add_amd:
case nir_intrinsic_buffer_atomic_add_amd:
case nir_intrinsic_load_rt_arg_scratch_offset_amd: case nir_intrinsic_load_rt_arg_scratch_offset_amd:
case nir_intrinsic_load_intersection_opaque_amd: case nir_intrinsic_load_intersection_opaque_amd:
case nir_intrinsic_load_vector_arg_amd: case nir_intrinsic_load_vector_arg_amd:

3
src/compiler/nir/nir_intrinsics.py
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@@ -1332,6 +1332,9 @@ store("global_amd", [1, 1], indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET, WRIT
# Same as shared_atomic_add, but with GDS. src[] = {store_val, gds_addr, m0} # Same as shared_atomic_add, but with GDS. src[] = {store_val, gds_addr, m0}
intrinsic("gds_atomic_add_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) intrinsic("gds_atomic_add_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE])
# src[] = { descriptor, add_value }
intrinsic("buffer_atomic_add_amd", src_comp=[4, 1], dest_comp=1, indices=[BASE])
# src[] = { sample_id, num_samples } # src[] = { sample_id, num_samples }
intrinsic("load_sample_positions_amd", src_comp=[1, 1], dest_comp=2, flags=[CAN_ELIMINATE, CAN_REORDER]) intrinsic("load_sample_positions_amd", src_comp=[1, 1], dest_comp=2, flags=[CAN_ELIMINATE, CAN_REORDER])