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intel/compiler: Pass shader_stats for each SIMD mode

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Passing shader_stats to the fs_generator constructor means that the
SIMD8 shader stats from the visitor (such as the scheduler mode) will be
reported out for the SIMD16/SIMD32 versions as well.

As you can see, we are now passing 'shader_stats' and 'stats' to
generate_code(), which is obviously odd looking. Ian rebased and
committed an old patch of mine which added the shader_stats struct on
July 30 in commit dabb5d4bee (i965/fs: Add a shader_stats struct.) and
shortly after on August 12 Jason added the brw_compile_stats struct in
commit 134607760a (intel/compiler: Fill a compiler statistics struct).

I'd like to combine the two, but I'm not sure how. shader_stats is an
input to generate_code() while brw_compile_stats is an output and is
only used by the Vulkan driver. Leave it as is for now...

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
This commit is contained in:
Matt Turner
2020-03-04 16:24:25 -08:00
committed by Marge Bot
parent e7d0460d58
commit bb3e7b0fe3
7 changed files with 21 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/intel/compiler/brw_fs.cpp
View File

@@ -8601,6 +8601,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
brw_compute_flat_inputs(prog_data, shader);
cfg_t *simd8_cfg = NULL, *simd16_cfg = NULL, *simd32_cfg = NULL;
struct shader_stats v8_shader_stats, v16_shader_stats, v32_shader_stats;
fs_visitor v8(compiler, log_data, mem_ctx, &key->base,
&prog_data->base, shader, 8,
@@ -8612,6 +8613,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
return NULL;
} else if (likely(!(INTEL_DEBUG & DEBUG_NO8))) {
simd8_cfg = v8.cfg;
v8_shader_stats = v8.shader_stats;
prog_data->base.dispatch_grf_start_reg = v8.payload.num_regs;
prog_data->reg_blocks_8 = brw_register_blocks(v8.grf_used);
}
@@ -8639,6 +8641,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
v16.fail_msg);
} else {
simd16_cfg = v16.cfg;
v16_shader_stats = v16.shader_stats;
prog_data->dispatch_grf_start_reg_16 = v16.payload.num_regs;
prog_data->reg_blocks_16 = brw_register_blocks(v16.grf_used);
}
@@ -8659,6 +8662,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
v32.fail_msg);
} else {
simd32_cfg = v32.cfg;
v32_shader_stats = v32.shader_stats;
prog_data->dispatch_grf_start_reg_32 = v32.payload.num_regs;
prog_data->reg_blocks_32 = brw_register_blocks(v32.grf_used);
}
@@ -8712,8 +8716,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
}
fs_generator g(compiler, log_data, mem_ctx, &prog_data->base,
v8.shader_stats, v8.runtime_check_aads_emit,
MESA_SHADER_FRAGMENT);
v8.runtime_check_aads_emit, MESA_SHADER_FRAGMENT);
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
g.enable_debug(ralloc_asprintf(mem_ctx, "%s fragment shader %s",
@@ -8724,19 +8727,19 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
if (simd8_cfg) {
prog_data->dispatch_8 = true;
g.generate_code(simd8_cfg, 8, stats);
g.generate_code(simd8_cfg, 8, v8_shader_stats, stats);
stats = stats ? stats + 1 : NULL;
}
if (simd16_cfg) {
prog_data->dispatch_16 = true;
prog_data->prog_offset_16 = g.generate_code(simd16_cfg, 16, stats);
prog_data->prog_offset_16 = g.generate_code(simd16_cfg, 16, v16_shader_stats, stats);
stats = stats ? stats + 1 : NULL;
}
if (simd32_cfg) {
prog_data->dispatch_32 = true;
prog_data->prog_offset_32 = g.generate_code(simd32_cfg, 32, stats);
prog_data->prog_offset_32 = g.generate_code(simd32_cfg, 32, v32_shader_stats, stats);
stats = stats ? stats + 1 : NULL;
}
@@ -8979,8 +8982,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
*error_str = ralloc_strdup(mem_ctx, fail_msg);
} else {
fs_generator g(compiler, log_data, mem_ctx, &prog_data->base,
v->shader_stats, v->runtime_check_aads_emit,
MESA_SHADER_COMPUTE);
v->runtime_check_aads_emit, MESA_SHADER_COMPUTE);
if (INTEL_DEBUG & DEBUG_CS) {
char *name = ralloc_asprintf(mem_ctx, "%s compute shader %s",
src_shader->info.label ?
@@ -8989,7 +8991,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
g.enable_debug(name);
}
g.generate_code(v->cfg, prog_data->simd_size, stats);
g.generate_code(v->cfg, prog_data->simd_size, v->shader_stats, stats);
ret = g.get_assembly();
}

3
src/intel/compiler/brw_fs.h
View File

@@ -467,13 +467,13 @@ public:
fs_generator(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
struct brw_stage_prog_data *prog_data,
struct shader_stats shader_stats,
bool runtime_check_aads_emit,
gl_shader_stage stage);
~fs_generator();
void enable_debug(const char *shader_name);
int generate_code(const cfg_t *cfg, int dispatch_width,
struct shader_stats shader_stats,
struct brw_compile_stats *stats);
const unsigned *get_assembly();
@@ -572,7 +572,6 @@ private:
unsigned dispatch_width; /**< 8, 16 or 32 */
exec_list discard_halt_patches;
struct shader_stats shader_stats;
bool runtime_check_aads_emit;
bool debug_flag;
const char *shader_name;

3
src/intel/compiler/brw_fs_generator.cpp
View File

@@ -186,14 +186,12 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
struct brw_stage_prog_data *prog_data,
struct shader_stats shader_stats,
bool runtime_check_aads_emit,
gl_shader_stage stage)
: compiler(compiler), log_data(log_data),
devinfo(compiler->devinfo),
prog_data(prog_data),
shader_stats(shader_stats),
runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
stage(stage), mem_ctx(mem_ctx)
{
@@ -1698,6 +1696,7 @@ fs_generator::enable_debug(const char *shader_name)
int
fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
struct shader_stats shader_stats,
struct brw_compile_stats *stats)
{
/* align to 64 byte boundary. */

5
src/intel/compiler/brw_shader.cpp
View File

@@ -1361,8 +1361,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_generator g(compiler, log_data, mem_ctx,
&prog_data->base.base, v.shader_stats, false,
MESA_SHADER_TESS_EVAL);
&prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
g.enable_debug(ralloc_asprintf(mem_ctx,
"%s tessellation evaluation shader %s",
@@ -1371,7 +1370,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
nir->info.name));
}
g.generate_code(v.cfg, 8, stats);
g.generate_code(v.cfg, 8, v.shader_stats, stats);
assembly = g.get_assembly();
} else {

6
src/intel/compiler/brw_vec4.cpp
View File

@@ -2988,8 +2988,8 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
fs_generator g(compiler, log_data, mem_ctx,
&prog_data->base.base, v.shader_stats,
v.runtime_check_aads_emit, MESA_SHADER_VERTEX);
&prog_data->base.base, v.runtime_check_aads_emit,
MESA_SHADER_VERTEX);
if (INTEL_DEBUG & DEBUG_VS) {
const char *debug_name =
ralloc_asprintf(mem_ctx, "%s vertex shader %s",
@@ -2999,7 +2999,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
g.enable_debug(debug_name);
}
g.generate_code(v.cfg, 8, stats);
g.generate_code(v.cfg, 8, v.shader_stats, stats);
assembly = g.get_assembly();
}

5
src/intel/compiler/brw_vec4_gs_visitor.cpp
View File

@@ -857,8 +857,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
fs_generator g(compiler, log_data, mem_ctx,
&prog_data->base.base, v.shader_stats,
false, MESA_SHADER_GEOMETRY);
&prog_data->base.base, false, MESA_SHADER_GEOMETRY);
if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
const char *label =
shader->info.label ? shader->info.label : "unnamed";
@@ -866,7 +865,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
label, shader->info.name);
g.enable_debug(name);
}
g.generate_code(v.cfg, 8, stats);
g.generate_code(v.cfg, 8, v.shader_stats, stats);
return g.get_assembly();
}
}

5
src/intel/compiler/brw_vec4_tcs.cpp
View File

@@ -441,8 +441,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
fs_generator g(compiler, log_data, mem_ctx,
&prog_data->base.base, v.shader_stats, false,
MESA_SHADER_TESS_CTRL);
&prog_data->base.base, false, MESA_SHADER_TESS_CTRL);
if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
g.enable_debug(ralloc_asprintf(mem_ctx,
"%s tessellation control shader %s",
@@ -451,7 +450,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
nir->info.name));
}
g.generate_code(v.cfg, 8, stats);
g.generate_code(v.cfg, 8, v.shader_stats, stats);
assembly = g.get_assembly();
} else {