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anv: implement undocumented tile cache flush requirements

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27169>
This commit is contained in:
Lionel Landwerlin
2024-01-18 10:08:55 +00:00
committed by Marge Bot
parent 0bc6462924
commit ba87656079
2 changed files with 40 additions and 0 deletions
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10
src/intel/vulkan/anv_private.h
View File

@@ -5014,6 +5014,16 @@ anv_image_has_private_binding(const struct anv_image *image)
return private_binding.memory_range.size != 0;
}
static inline bool
anv_image_format_is_d16_or_s8(const struct anv_image *image)
{
return image->vk.format == VK_FORMAT_D16_UNORM ||
image->vk.format == VK_FORMAT_D16_UNORM_S8_UINT ||
image->vk.format == VK_FORMAT_D24_UNORM_S8_UINT ||
image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
image->vk.format == VK_FORMAT_S8_UINT;
}
/* The ordering of this enum is important */
enum anv_fast_clear_type {
/** Image does not have/support any fast-clear blocks */

30
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -394,6 +394,23 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, base_layer, layer_count, ISL_AUX_OP_AMBIGUATE);
}
#if GFX_VER == 12
/* Depth/Stencil writes by the render pipeline to D16 & S8 formats use a
* different pairing bit for the compression cache line. This means that
* there is potential for aliasing with the wrong cache if you use another
* format OR a piece of HW that does not use the same pairing. To avoid
* this, flush the tile cache as the compression data does not live in the
* color/depth cache.
*/
if (image->planes[depth_plane].aux_usage == ISL_AUX_USAGE_HIZ_CCS &&
final_needs_depth && !initial_depth_valid &&
anv_image_format_is_d16_or_s8(image)) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_TILE_CACHE_FLUSH_BIT,
"D16 or S8 HIZ-CCS flush");
}
#endif
}
/* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
@@ -449,6 +466,19 @@ transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer,
clear_rect, 0 /* Stencil clear value */);
}
}
/* Depth/Stencil writes by the render pipeline to D16 & S8 formats use a
* different pairing bit for the compression cache line. This means that
* there is potential for aliasing with the wrong cache if you use another
* format OR a piece of HW that does not use the same pairing. To avoid
* this, flush the tile cache as the compression data does not live in the
* color/depth cache.
*/
if (anv_image_format_is_d16_or_s8(image)) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_TILE_CACHE_FLUSH_BIT,
"D16 or S8 HIZ-CCS flush");
}
#endif
}