diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 65045f1c6a0..8a1d0f6d3f4 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -889,7 +889,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
 
    struct GENX(BLEND_STATE) blend_state = {
       .AlphaToCoverageEnable = ms && ms->alpha_to_coverage_enable,
-      .AlphaToOneEnable = ms && ms->alpha_to_one_enable,
    };
 
    uint32_t surface_count = 0;
diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c
index efbaca326c4..5059ab10662 100644
--- a/src/intel/vulkan/gfx8_cmd_buffer.c
+++ b/src/intel/vulkan/gfx8_cmd_buffer.c
@@ -520,7 +520,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
    if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) ||
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP) ||
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) ||
-       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE)) {
+       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE) ||
+       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_ALPHA_TO_ONE_ENABLE)) {
       const uint8_t color_writes = dyn->cb.color_write_enables;
       const struct anv_cmd_graphics_state *state = &cmd_buffer->state.gfx;
       bool has_writeable_rt =
@@ -546,7 +547,12 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       uint32_t *dws = blend_dws;
       memset(blend_dws, 0, sizeof(blend_dws));
 
-      /* Skip this part */
+      struct GENX(BLEND_STATE) blend_state = {
+         .AlphaToOneEnable = dyn->ms.alpha_to_one_enable,
+      };
+      GENX(BLEND_STATE_pack)(NULL, dws, &blend_state);
+
+      /* Jump to blend entries. */
       dws += GENX(BLEND_STATE_length);
 
       for (uint32_t i = 0; i < MAX_RTS; i++) {