anv: dynamic alpha to one enable
This affects following packets: BLEND_STATE Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18879>
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@@ -889,7 +889,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
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struct GENX(BLEND_STATE) blend_state = {
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.AlphaToCoverageEnable = ms && ms->alpha_to_coverage_enable,
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.AlphaToOneEnable = ms && ms->alpha_to_one_enable,
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};
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uint32_t surface_count = 0;
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@@ -520,7 +520,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE)) {
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_ALPHA_TO_ONE_ENABLE)) {
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const uint8_t color_writes = dyn->cb.color_write_enables;
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const struct anv_cmd_graphics_state *state = &cmd_buffer->state.gfx;
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bool has_writeable_rt =
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@@ -546,7 +547,12 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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uint32_t *dws = blend_dws;
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memset(blend_dws, 0, sizeof(blend_dws));
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/* Skip this part */
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struct GENX(BLEND_STATE) blend_state = {
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.AlphaToOneEnable = dyn->ms.alpha_to_one_enable,
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};
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GENX(BLEND_STATE_pack)(NULL, dws, &blend_state);
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/* Jump to blend entries. */
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dws += GENX(BLEND_STATE_length);
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for (uint32_t i = 0; i < MAX_RTS; i++) {
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