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aco: implement missing nir_op_unpack_half_2x16_split_{x,y}_flush_to_zero

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SPIRV->NIR emits nir_op_unpack_half_2x16_flush_to_zero instead of
nir_op_unpack_half_2x16 if the shader enables denorm flush to zero
for 16-bit floating point.

This doesn't fix anything known and CTS doesn't have tests.

Fixes: 56d9bcdded ("radv: enable more float_controls features")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6939>
This commit is contained in:
Samuel Pitoiset
2020-09-30 15:41:00 +02:00
parent 1070bba19e
commit b9ca4923d6
1 changed files with 4 additions and 0 deletions
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4
src/amd/compiler/aco_instruction_selection.cpp
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@@ -2628,16 +2628,20 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
break;
}
case nir_op_unpack_half_2x16_split_x_flush_to_zero:
case nir_op_unpack_half_2x16_split_x: {
if (dst.regClass() == v1) {
assert(ctx->block->fp_mode.must_flush_denorms16_64 == (instr->op == nir_op_unpack_half_2x16_split_x_flush_to_zero));
bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
} else {
isel_err(&instr->instr, "Unimplemented NIR instr bit size");
}
break;
}
case nir_op_unpack_half_2x16_split_y_flush_to_zero:
case nir_op_unpack_half_2x16_split_y: {
if (dst.regClass() == v1) {
assert(ctx->block->fp_mode.must_flush_denorms16_64 == (instr->op == nir_op_unpack_half_2x16_split_y_flush_to_zero));
/* TODO: use SDWA here */
bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));