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freedreno/ir3: Tweak ldib/resinfo encoding

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The blob is using '0' for the low bit in these (except for ldib where it
seems to randomly use either '0' or '1').  The upcoming xml based ISA
spec maps this bit to 'dontcare' in the ldib case.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
This commit is contained in:
Rob Clark
2020-12-21 11:08:05 -08:00
committed by Marge Bot
parent 99908c8d6d
commit b91319d952
1 changed files with 1 additions and 5 deletions
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6
src/freedreno/ir3/ir3.c
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@@ -653,13 +653,9 @@ static int emit_cat6_a6xx(struct ir3_instruction *instr, void *ptr,
cat6->pad5 = 0x3;
break;
case OPC_STIB:
cat6->pad1 = 0x0;
cat6->pad3 = 0x6;
cat6->pad5 = 0x2;
break;
case OPC_LDIB:
case OPC_RESINFO:
cat6->pad1 = 0x1;
cat6->pad1 = 0x0;
cat6->pad3 = 0x6;
cat6->pad5 = 0x2;
break;