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nir/algebraic: Separate has_dot_4x8 into has_sdot_4x8 and has_udot_4x8

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Adreno GPUs has native instruction for unsigned and mixed dot_4x8 but
not signed dot product.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13986>
This commit is contained in:
Danylo Piliaiev
2021-11-26 19:27:03 +02:00
parent c1d5c318bc
commit b8d486f298
6 changed files with 16 additions and 10 deletions
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3
src/intel/compiler/brw_compiler.c
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@@ -178,7 +178,8 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_options->lower_bitfield_reverse = devinfo->ver < 7;
nir_options->has_iadd3 = devinfo->verx10 >= 125;
nir_options->has_dot_4x8 = devinfo->ver >= 12;
nir_options->has_sdot_4x8 = devinfo->ver >= 12;
nir_options->has_udot_4x8 = devinfo->ver >= 12;
nir_options->has_sudot_4x8 = devinfo->ver >= 12;
nir_options->lower_int64_options = int64_options;