r600: add beginnings of ARL instruction
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@@ -355,6 +355,7 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm)
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return 2;
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case SQ_OP2_INST_MOV:
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case SQ_OP2_INST_MOVA_FLOOR:
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case SQ_OP2_INST_FRACT:
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case SQ_OP2_INST_FLOOR:
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case SQ_OP2_INST_EXP_IEEE:
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@@ -2064,7 +2065,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm)
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}
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//other bits
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alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_LOOP;
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alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_AR_X;
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if( (is_single_scalar_operation == GL_TRUE)
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|| (GL_TRUE == bSplitInst) )
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@@ -2398,6 +2399,35 @@ GLboolean assemble_ADD(r700_AssemblerBase *pAsm)
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return GL_TRUE;
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}
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GLboolean assemble_ARL(r700_AssemblerBase *pAsm)
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{ /* TODO: ar values dont' persist between clauses */
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if( GL_FALSE == checkop1(pAsm) )
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{
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return GL_FALSE;
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}
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pAsm->D.dst.opcode = SQ_OP2_INST_MOVA_FLOOR;
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setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
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pAsm->D.dst.rtype = DST_REG_TEMPORARY;
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pAsm->D.dst.reg = 0;
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pAsm->D.dst.writex = 0;
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pAsm->D.dst.writey = 0;
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pAsm->D.dst.writez = 0;
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pAsm->D.dst.writew = 0;
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if( GL_FALSE == assemble_src(pAsm, 0, -1) )
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{
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return GL_FALSE;
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}
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if( GL_FALSE == next_ins(pAsm) )
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{
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return GL_FALSE;
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}
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return GL_TRUE;
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}
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GLboolean assemble_BAD(char *opcode_str)
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{
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radeon_error("Not yet implemented instruction (%s)\n", opcode_str);
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@@ -3812,8 +3842,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts,
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break;
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case OPCODE_ARL:
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radeon_error("Not yet implemented instruction OPCODE_ARL \n");
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//if ( GL_FALSE == assemble_BAD("ARL") )
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if ( GL_FALSE == assemble_ARL(pR700AsmCode) )
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return GL_FALSE;
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break;
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case OPCODE_ARR:
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@@ -461,6 +461,7 @@ GLboolean next_ins(r700_AssemblerBase *pAsm);
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GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode);
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GLboolean assemble_ABS(r700_AssemblerBase *pAsm);
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GLboolean assemble_ADD(r700_AssemblerBase *pAsm);
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GLboolean assemble_ARL(r700_AssemblerBase *pAsm);
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GLboolean assemble_BAD(char *opcode_str);
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GLboolean assemble_CMP(r700_AssemblerBase *pAsm);
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GLboolean assemble_COS(r700_AssemblerBase *pAsm);
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