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radv: make sure to set CB_SHADER_MASK correctly for internal CB operations

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It should be always set to 0xf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5427>
This commit is contained in:
Samuel Pitoiset
2020-06-11 15:39:46 +02:00
committed by Marge Bot
parent 270eeb4105
commit b848d88059
1 changed files with 11 additions and 0 deletions
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11
src/amd/vulkan/radv_pipeline.c
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@@ -5119,6 +5119,17 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
}
if (extra &&
(extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
/* According to the CB spec states, CB_SHADER_MASK should be
* set to enable writes to all four channels of MRT0.
*/
blend.cb_shader_mask = 0xf;
}
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
if (pipeline->shaders[i]) {
pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;