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amd/registers: switch to new generated register definitions

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Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6423>
This commit is contained in:
Marek Olšák
2020-08-21 08:09:58 -04:00
parent e492a3195c
commit b7a6333ee4
22 changed files with 11165 additions and 32326 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/amd/Android.common.mk
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@@ -59,10 +59,16 @@ $(intermediates)/common/sid_tables.h: $(SID_TABLES) $(SID_TABLES_INPUTS)
AMDGFXREGS := $(LOCAL_PATH)/registers/makeregheader.py AMDGFXREGS := $(LOCAL_PATH)/registers/makeregheader.py
AMDGFXREGS_INPUTS := \ AMDGFXREGS_INPUTS := \
$(LOCAL_PATH)/registers/amdgfxregs.json \ $(LOCAL_PATH)/registers/gfx6.json \
$(LOCAL_PATH)/registers/pkt3.json \ $(LOCAL_PATH)/registers/gfx7.json \
$(LOCAL_PATH)/registers/gfx8.json \
$(LOCAL_PATH)/registers/gfx81.json \
$(LOCAL_PATH)/registers/gfx9.json \
$(LOCAL_PATH)/registers/gfx10.json \ $(LOCAL_PATH)/registers/gfx10.json \
$(LOCAL_PATH)/registers/gfx10-rsrc.json $(LOCAL_PATH)/registers/gfx103.json \
$(LOCAL_PATH)/registers/pkt3.json \
$(LOCAL_PATH)/registers/gfx10-rsrc.json \
$(LOCAL_PATH)/registers/registers-manually-defined.json
$(intermediates)/common/amdgfxregs.h: $(AMDGFXREGS) $(AMDGFXREGS_INPUTS) $(intermediates)/common/amdgfxregs.h: $(AMDGFXREGS) $(AMDGFXREGS_INPUTS)
@mkdir -p $(dir $@) @mkdir -p $(dir $@)

2
src/amd/common/ac_gpu_info.c
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@@ -1305,7 +1305,7 @@ unsigned ac_get_compute_resource_limits(struct radeon_info *info,
/* GFX6 */ /* GFX6 */
if (max_waves_per_sh) { if (max_waves_per_sh) {
unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16); unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16); compute_resource_limits |= S_00B854_WAVES_PER_SH_GFX6(limit_div16);
} }
} }
return compute_resource_limits; return compute_resource_limits;

8
src/amd/common/ac_shadowed_regs.c
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@@ -637,8 +637,8 @@ static const struct ac_reg_range Gfx103ContextShadowRange[] = {
R_028714_SPI_SHADER_COL_FORMAT - R_028644_SPI_PS_INPUT_CNTL_0 + 4, R_028714_SPI_SHADER_COL_FORMAT - R_028644_SPI_PS_INPUT_CNTL_0 + 4,
}, },
{ {
R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, R_028750_SX_PS_DOWNCONVERT_CONTROL,
R_02879C_CB_BLEND7_CONTROL - R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103 + 4, R_02879C_CB_BLEND7_CONTROL - R_028750_SX_PS_DOWNCONVERT_CONTROL + 4,
}, },
{ {
R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
@@ -787,7 +787,7 @@ static const struct ac_reg_range Gfx103NonShadowedRanges[] = {
/* SQ thread trace registers are always not shadowed. */ /* SQ thread trace registers are always not shadowed. */
{ {
R_008D00_SQ_THREAD_TRACE_BUF0_BASE, R_008D00_SQ_THREAD_TRACE_BUF0_BASE,
R_008D3C_SQ_THREAD_TRACE_STATUS2_GFX103 - R_008D00_SQ_THREAD_TRACE_BUF0_BASE + 4, R_008D3C_SQ_THREAD_TRACE_STATUS2 - R_008D00_SQ_THREAD_TRACE_BUF0_BASE + 4,
}, },
{ {
R_030D00_SQ_THREAD_TRACE_USERDATA_0, R_030D00_SQ_THREAD_TRACE_USERDATA_0,
@@ -2893,7 +2893,7 @@ static void gfx103_emulate_clear_state(struct radeon_cmdbuf *cs, unsigned num_re
set_context_reg_seq_array(cs, R_0281E8_COHER_DEST_BASE_HI_0, SET(CoherDestBaseHi0Gfx103)); set_context_reg_seq_array(cs, R_0281E8_COHER_DEST_BASE_HI_0, SET(CoherDestBaseHi0Gfx103));
set_context_reg_seq_array(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, SET(VgtMultiPrimIbResetIndxGfx103)); set_context_reg_seq_array(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, SET(VgtMultiPrimIbResetIndxGfx103));
set_context_reg_seq_array(cs, R_028644_SPI_PS_INPUT_CNTL_0, SET(SpiPsInputCntl0Gfx103)); set_context_reg_seq_array(cs, R_028644_SPI_PS_INPUT_CNTL_0, SET(SpiPsInputCntl0Gfx103));
set_context_reg_seq_array(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, SET(SxPsDownconvertControlGfx103)); set_context_reg_seq_array(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL, SET(SxPsDownconvertControlGfx103));
set_context_reg_seq_array(cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, SET(GeMaxOutputPerSubgroupGfx103)); set_context_reg_seq_array(cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, SET(GeMaxOutputPerSubgroupGfx103));
set_context_reg_seq_array(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, SET(PaSuPrimFilterCntlGfx103)); set_context_reg_seq_array(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, SET(PaSuPrimFilterCntlGfx103));
set_context_reg_seq_array(cs, R_028A00_PA_SU_POINT_SIZE, SET(PaSuPointSizeGfx103)); set_context_reg_seq_array(cs, R_028A00_PA_SU_POINT_SIZE, SET(PaSuPointSizeGfx103));

22
src/amd/common/meson.build
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@@ -18,10 +18,25 @@
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE. # SOFTWARE.
amd_json_files = [
# Generated:
'../registers/gfx6.json',
'../registers/gfx7.json',
'../registers/gfx8.json',
'../registers/gfx81.json',
'../registers/gfx9.json',
'../registers/gfx10.json',
'../registers/gfx103.json',
# Manually written:
'../registers/pkt3.json',
'../registers/gfx10-rsrc.json',
'../registers/registers-manually-defined.json',
]
sid_tables_h = custom_target( sid_tables_h = custom_target(
'sid_tables_h', 'sid_tables_h',
input : ['sid_tables.py', 'sid.h', '../registers/amdgfxregs.json', '../registers/pkt3.json', input : ['sid_tables.py', 'sid.h'] + amd_json_files,
'../registers/gfx10.json', '../registers/gfx10-rsrc.json'],
output : 'sid_tables.h', output : 'sid_tables.h',
command : [prog_python, '@INPUT@'], command : [prog_python, '@INPUT@'],
capture : true, capture : true,
@@ -29,8 +44,7 @@ sid_tables_h = custom_target(
amdgfxregs_h = custom_target( amdgfxregs_h = custom_target(
'amdgfxregs_h', 'amdgfxregs_h',
input : ['../registers/makeregheader.py', '../registers/amdgfxregs.json', '../registers/pkt3.json', input : ['../registers/makeregheader.py'] + amd_json_files,
'../registers/gfx10.json', '../registers/gfx10-rsrc.json'],
output : 'amdgfxregs.h', output : 'amdgfxregs.h',
command : [prog_python, '@INPUT@', '--sort', 'address', '--guard', 'AMDGFXREGS_H'], command : [prog_python, '@INPUT@', '--sort', 'address', '--guard', 'AMDGFXREGS_H'],
capture : true, capture : true,

16176
src/amd/registers/amdgfxregs.json
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File diff suppressed because it is too large Load Diff

34
src/amd/registers/gfx10-rsrc.json
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@@ -195,99 +195,99 @@
}, },
"register_mappings": [ "register_mappings": [
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 36608, "to": "mm"}, "map": {"at": 36608, "to": "mm"},
"name": "SQ_BUF_RSRC_WORD0" "name": "SQ_BUF_RSRC_WORD0"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 36612, "to": "mm"}, "map": {"at": 36612, "to": "mm"},
"name": "SQ_BUF_RSRC_WORD1", "name": "SQ_BUF_RSRC_WORD1",
"type_ref": "SQ_BUF_RSRC_WORD1" "type_ref": "SQ_BUF_RSRC_WORD1"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 36616, "to": "mm"}, "map": {"at": 36616, "to": "mm"},
"name": "SQ_BUF_RSRC_WORD2" "name": "SQ_BUF_RSRC_WORD2"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 36620, "to": "mm"}, "map": {"at": 36620, "to": "mm"},
"name": "SQ_BUF_RSRC_WORD3", "name": "SQ_BUF_RSRC_WORD3",
"type_ref": "SQ_BUF_RSRC_WORD3" "type_ref": "SQ_BUF_RSRC_WORD3"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 36348, "to": "mm"}, "map": {"at": 36348, "to": "mm"},
"name": "SQ_EXP_0", "name": "SQ_EXP_0",
"type_ref": "SQ_EXP_0" "type_ref": "SQ_EXP_0"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 40960, "to": "mm"}, "map": {"at": 40960, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD0" "name": "SQ_IMG_RSRC_WORD0"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 40964, "to": "mm"}, "map": {"at": 40964, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD1", "name": "SQ_IMG_RSRC_WORD1",
"type_ref": "SQ_IMG_RSRC_WORD1" "type_ref": "SQ_IMG_RSRC_WORD1"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 40968, "to": "mm"}, "map": {"at": 40968, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD2", "name": "SQ_IMG_RSRC_WORD2",
"type_ref": "SQ_IMG_RSRC_WORD2" "type_ref": "SQ_IMG_RSRC_WORD2"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 40972, "to": "mm"}, "map": {"at": 40972, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD3", "name": "SQ_IMG_RSRC_WORD3",
"type_ref": "SQ_IMG_RSRC_WORD3" "type_ref": "SQ_IMG_RSRC_WORD3"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 40976, "to": "mm"}, "map": {"at": 40976, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD4", "name": "SQ_IMG_RSRC_WORD4",
"type_ref": "SQ_IMG_RSRC_WORD4" "type_ref": "SQ_IMG_RSRC_WORD4"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 40980, "to": "mm"}, "map": {"at": 40980, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD5", "name": "SQ_IMG_RSRC_WORD5",
"type_ref": "SQ_IMG_RSRC_WORD5" "type_ref": "SQ_IMG_RSRC_WORD5"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 40984, "to": "mm"}, "map": {"at": 40984, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD6", "name": "SQ_IMG_RSRC_WORD6",
"type_ref": "SQ_IMG_RSRC_WORD6" "type_ref": "SQ_IMG_RSRC_WORD6"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 40988, "to": "mm"}, "map": {"at": 40988, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD7" "name": "SQ_IMG_RSRC_WORD7"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 36656, "to": "mm"}, "map": {"at": 36656, "to": "mm"},
"name": "SQ_IMG_SAMP_WORD0", "name": "SQ_IMG_SAMP_WORD0",
"type_ref": "SQ_IMG_SAMP_WORD0" "type_ref": "SQ_IMG_SAMP_WORD0"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 36660, "to": "mm"}, "map": {"at": 36660, "to": "mm"},
"name": "SQ_IMG_SAMP_WORD1", "name": "SQ_IMG_SAMP_WORD1",
"type_ref": "SQ_IMG_SAMP_WORD1" "type_ref": "SQ_IMG_SAMP_WORD1"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 36664, "to": "mm"}, "map": {"at": 36664, "to": "mm"},
"name": "SQ_IMG_SAMP_WORD2", "name": "SQ_IMG_SAMP_WORD2",
"type_ref": "SQ_IMG_SAMP_WORD2" "type_ref": "SQ_IMG_SAMP_WORD2"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 36668, "to": "mm"}, "map": {"at": 36668, "to": "mm"},
"name": "SQ_IMG_SAMP_WORD3", "name": "SQ_IMG_SAMP_WORD3",
"type_ref": "SQ_IMG_SAMP_WORD3" "type_ref": "SQ_IMG_SAMP_WORD3"

26976
src/amd/registers/gfx10.json
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File diff suppressed because it is too large Load Diff

4
src/amd/registers/makeregheader.py
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@@ -46,10 +46,10 @@ CHIPS = [
Object(name='gfx6', disambiguation='GFX6'), Object(name='gfx6', disambiguation='GFX6'),
Object(name='gfx7', disambiguation='GFX7'), Object(name='gfx7', disambiguation='GFX7'),
Object(name='gfx8', disambiguation='GFX8'), Object(name='gfx8', disambiguation='GFX8'),
Object(name='fiji', disambiguation='GFX8'), Object(name='gfx81', disambiguation='GFX81'),
Object(name='stoney', disambiguation='GFX8'),
Object(name='gfx9', disambiguation='GFX9'), Object(name='gfx9', disambiguation='GFX9'),
Object(name='gfx10', disambiguation='GFX10'), Object(name='gfx10', disambiguation='GFX10'),
Object(name='gfx103', disambiguation='GFX103'),
] ]
######### END HARDCODED CONFIGURATION ######### END HARDCODED CONFIGURATION

42
src/amd/registers/pkt3.json
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@@ -122,13 +122,13 @@
}, },
"register_mappings": [ "register_mappings": [
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81"],
"map": {"at": 1044, "to": "pkt3"}, "map": {"at": 1044, "to": "pkt3"},
"name": "COMMAND", "name": "COMMAND",
"type_ref": "COMMAND" "type_ref": "COMMAND"
}, },
{ {
"chips": ["gfx9", "gfx10"], "chips": ["gfx9", "gfx10", "gfx103"],
"map": {"at": 1044, "to": "pkt3"}, "map": {"at": 1044, "to": "pkt3"},
"name": "COMMAND", "name": "COMMAND",
"type_ref": "COMMAND_gfx9" "type_ref": "COMMAND_gfx9"
@@ -140,13 +140,13 @@
"type_ref": "CONTROL" "type_ref": "CONTROL"
}, },
{ {
"chips": ["gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 880, "to": "pkt3"}, "map": {"at": 880, "to": "pkt3"},
"name": "CONTROL", "name": "CONTROL",
"type_ref": "CONTROL_cik" "type_ref": "CONTROL_cik"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1040, "to": "pkt3"}, "map": {"at": 1040, "to": "pkt3"},
"name": "CP_DMA_WORD0", "name": "CP_DMA_WORD0",
"type_ref": "CP_DMA_WORD0" "type_ref": "CP_DMA_WORD0"
@@ -158,25 +158,25 @@
"type_ref": "CP_DMA_WORD1" "type_ref": "CP_DMA_WORD1"
}, },
{ {
"chips": ["gfx7", "gfx8", "fiji", "stoney"], "chips": ["gfx7", "gfx8", "gfx81"],
"map": {"at": 1041, "to": "pkt3"}, "map": {"at": 1041, "to": "pkt3"},
"name": "CP_DMA_WORD1", "name": "CP_DMA_WORD1",
"type_ref": "CP_DMA_WORD1_cik" "type_ref": "CP_DMA_WORD1_cik"
}, },
{ {
"chips": ["gfx9", "gfx10"], "chips": ["gfx9", "gfx10", "gfx103"],
"map": {"at": 1041, "to": "pkt3"}, "map": {"at": 1041, "to": "pkt3"},
"name": "CP_DMA_WORD1", "name": "CP_DMA_WORD1",
"type_ref": "CP_DMA_WORD1_gfx9" "type_ref": "CP_DMA_WORD1_gfx9"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1042, "to": "pkt3"}, "map": {"at": 1042, "to": "pkt3"},
"name": "CP_DMA_WORD2", "name": "CP_DMA_WORD2",
"type_ref": "CP_DMA_WORD2" "type_ref": "CP_DMA_WORD2"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1043, "to": "pkt3"}, "map": {"at": 1043, "to": "pkt3"},
"name": "CP_DMA_WORD3", "name": "CP_DMA_WORD3",
"type_ref": "CP_DMA_WORD3" "type_ref": "CP_DMA_WORD3"
@@ -188,72 +188,72 @@
"type_ref": "DMA_DATA_WORD0" "type_ref": "DMA_DATA_WORD0"
}, },
{ {
"chips": ["gfx7", "gfx8", "fiji", "stoney"], "chips": ["gfx7", "gfx8", "gfx81"],
"map": {"at": 1280, "to": "pkt3"}, "map": {"at": 1280, "to": "pkt3"},
"name": "DMA_DATA_WORD0", "name": "DMA_DATA_WORD0",
"type_ref": "DMA_DATA_WORD0_cik" "type_ref": "DMA_DATA_WORD0_cik"
}, },
{ {
"chips": ["gfx9", "gfx10"], "chips": ["gfx9", "gfx10", "gfx103"],
"map": {"at": 1280, "to": "pkt3"}, "map": {"at": 1280, "to": "pkt3"},
"name": "DMA_DATA_WORD0", "name": "DMA_DATA_WORD0",
"type_ref": "DMA_DATA_WORD0_gfx9" "type_ref": "DMA_DATA_WORD0_gfx9"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 882, "to": "pkt3"}, "map": {"at": 882, "to": "pkt3"},
"name": "DST_ADDR_HI" "name": "DST_ADDR_HI"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1284, "to": "pkt3"}, "map": {"at": 1284, "to": "pkt3"},
"name": "DST_ADDR_HI" "name": "DST_ADDR_HI"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 881, "to": "pkt3"}, "map": {"at": 881, "to": "pkt3"},
"name": "DST_ADDR_LO" "name": "DST_ADDR_LO"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1283, "to": "pkt3"}, "map": {"at": 1283, "to": "pkt3"},
"name": "DST_ADDR_LO" "name": "DST_ADDR_LO"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 1414, "to": "pkt3"}, "map": {"at": 1414, "to": "pkt3"},
"name": "GCR_CNTL", "name": "GCR_CNTL",
"type_ref": "GCR_CNTL" "type_ref": "GCR_CNTL"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1009, "to": "pkt3"}, "map": {"at": 1009, "to": "pkt3"},
"name": "IB_BASE_HI" "name": "IB_BASE_HI"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1008, "to": "pkt3"}, "map": {"at": 1008, "to": "pkt3"},
"name": "IB_BASE_LO" "name": "IB_BASE_LO"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1010, "to": "pkt3"}, "map": {"at": 1010, "to": "pkt3"},
"name": "IB_CONTROL", "name": "IB_CONTROL",
"type_ref": "IB_CONTROL" "type_ref": "IB_CONTROL"
}, },
{ {
"chips": ["gfx10"], "chips": ["gfx10", "gfx103"],
"map": {"at": 1168, "to": "pkt3"}, "map": {"at": 1168, "to": "pkt3"},
"name": "RELEASE_MEM_OP", "name": "RELEASE_MEM_OP",
"type_ref": "RELEASE_MEM_OP" "type_ref": "RELEASE_MEM_OP"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1282, "to": "pkt3"}, "map": {"at": 1282, "to": "pkt3"},
"name": "SRC_ADDR_HI" "name": "SRC_ADDR_HI"
}, },
{ {
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"], "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
"map": {"at": 1281, "to": "pkt3"}, "map": {"at": 1281, "to": "pkt3"},
"name": "SRC_ADDR_LO" "name": "SRC_ADDR_LO"
} }

22
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1746,8 +1746,8 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */ meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */ meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
} else { } else {
meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */ meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */ meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */
} }
bool zs_big_page = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 && bool zs_big_page = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
@@ -1772,12 +1772,12 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32); radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
radeon_emit(cmd_buffer->cs, radeon_emit(cmd_buffer->cs,
S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) | S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) | S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_HTILE_WR_POLICY(meta_write_policy) | S_02807C_HTILE_WR_POLICY(meta_write_policy) |
S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) | S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) | S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) |
S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) | S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) |
S_02807C_HTILE_RD_POLICY(meta_read_policy) | S_02807C_HTILE_RD_POLICY(meta_read_policy) |
S_02807C_Z_BIG_PAGE(zs_big_page) | S_02807C_Z_BIG_PAGE(zs_big_page) |
S_02807C_S_BIG_PAGE(zs_big_page)); S_02807C_S_BIG_PAGE(zs_big_page));
@@ -2336,19 +2336,19 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */ meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */ meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
} else { } else {
meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */ meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */ meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */
} }
radeon_set_context_reg(cmd_buffer->cs, R_028410_CB_RMI_GL2_CACHE_CONTROL, radeon_set_context_reg(cmd_buffer->cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
S_028410_CMASK_WR_POLICY(meta_write_policy) | S_028410_CMASK_WR_POLICY(meta_write_policy) |
S_028410_FMASK_WR_POLICY(meta_write_policy) | S_028410_FMASK_WR_POLICY(meta_write_policy) |
S_028410_DCC_WR_POLICY(meta_write_policy) | S_028410_DCC_WR_POLICY(meta_write_policy) |
S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) | S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM) |
S_028410_CMASK_RD_POLICY(meta_read_policy) | S_028410_CMASK_RD_POLICY(meta_read_policy) |
S_028410_FMASK_RD_POLICY(meta_read_policy) | S_028410_FMASK_RD_POLICY(meta_read_policy) |
S_028410_DCC_RD_POLICY(meta_read_policy) | S_028410_DCC_RD_POLICY(meta_read_policy) |
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD) | S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA) |
S_028410_FMASK_BIG_PAGE(color_big_page) | S_028410_FMASK_BIG_PAGE(color_big_page) |
S_028410_COLOR_BIG_PAGE(color_big_page)); S_028410_COLOR_BIG_PAGE(color_big_page));
} }

19
src/amd/vulkan/radv_debug.c
View File

@@ -765,14 +765,25 @@ radv_dump_sq_hw_regs(struct radv_device *device)
struct radv_sq_hw_reg *regs = (struct radv_sq_hw_reg *)&device->tma_ptr[6]; struct radv_sq_hw_reg *regs = (struct radv_sq_hw_reg *)&device->tma_ptr[6];
fprintf(stderr, "\nHardware registers:\n"); fprintf(stderr, "\nHardware registers:\n");
if (device->physical_device->rad_info.chip_class >= GFX10) {
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
R_000002_SQ_HW_REG_STATUS, regs->status, ~0); R_000408_SQ_WAVE_STATUS, regs->status, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
R_000003_SQ_HW_REG_TRAP_STS, regs->trap_sts, ~0); R_00040C_SQ_WAVE_TRAPSTS, regs->trap_sts, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
R_000004_SQ_HW_REG_HW_ID, regs->hw_id, ~0); R_00045C_SQ_WAVE_HW_ID1, regs->hw_id, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
R_000007_SQ_HW_REG_IB_STS, regs->ib_sts, ~0); R_00041C_SQ_WAVE_IB_STS, regs->ib_sts, ~0);
} else {
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
R_000048_SQ_WAVE_STATUS, regs->status, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
R_00004C_SQ_WAVE_TRAPSTS, regs->trap_sts, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
R_000050_SQ_WAVE_HW_ID, regs->hw_id, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class,
R_00005C_SQ_WAVE_IB_STS, regs->ib_sts, ~0);
}
fprintf(stderr, "\n\n"); fprintf(stderr, "\n\n");
} }

6
src/amd/vulkan/radv_device.c
View File

@@ -3281,8 +3281,8 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff
if (device->physical_device->rad_info.chip_class >= GFX8) if (device->physical_device->rad_info.chip_class >= GFX8)
--max_offchip_buffers; --max_offchip_buffers;
hs_offchip_param = hs_offchip_param =
S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) | S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) |
S_03093C_OFFCHIP_GRANULARITY(offchip_granularity); S_03093C_OFFCHIP_GRANULARITY_GFX7(offchip_granularity);
} else { } else {
hs_offchip_param = hs_offchip_param =
S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
@@ -7419,7 +7419,7 @@ radv_init_sampler(struct radv_device *device,
sampler->state[2] |= sampler->state[2] |=
S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) | S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
S_008F38_FILTER_PREC_FIX(1) | S_008F38_FILTER_PREC_FIX(1) |
S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8); S_008F38_ANISO_OVERRIDE_GFX8(device->physical_device->rad_info.chip_class >= GFX8);
} }
} }

6
src/amd/vulkan/radv_image.c
View File

@@ -1032,13 +1032,13 @@ si_make_texture_descriptor(struct radv_device *device,
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK; fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
switch (image->info.samples) { switch (image->info.samples) {
case 2: case 2:
num_format = V_008F14_IMG_FMASK_8_2_2; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_2;
break; break;
case 4: case 4:
num_format = V_008F14_IMG_FMASK_8_4_4; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_4;
break; break;
case 8: case 8:
num_format = V_008F14_IMG_FMASK_32_8_8; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_8_8;
break; break;
default: default:
unreachable("invalid nr_samples"); unreachable("invalid nr_samples");

42
src/amd/vulkan/radv_pipeline.c
View File

@@ -1176,7 +1176,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) | ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) | S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */ S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3); S_028BE0_COVERED_CENTROID_IS_CENTER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
if (ps_iter_samples > 1) if (ps_iter_samples > 1)
pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
@@ -1217,18 +1217,18 @@ si_conv_gl_prim_to_gs_out(unsigned gl_prim)
{ {
switch (gl_prim) { switch (gl_prim) {
case 0: /* GL_POINTS */ case 0: /* GL_POINTS */
return V_028A6C_OUTPRIM_TYPE_POINTLIST; return V_028A6C_POINTLIST;
case 1: /* GL_LINES */ case 1: /* GL_LINES */
case 3: /* GL_LINE_STRIP */ case 3: /* GL_LINE_STRIP */
case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */ case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
case 0x8E7A: /* GL_ISOLINES */ case 0x8E7A: /* GL_ISOLINES */
return V_028A6C_OUTPRIM_TYPE_LINESTRIP; return V_028A6C_LINESTRIP;
case 4: /* GL_TRIANGLES */ case 4: /* GL_TRIANGLES */
case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */ case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
case 5: /* GL_TRIANGLE_STRIP */ case 5: /* GL_TRIANGLE_STRIP */
case 7: /* GL_QUADS */ case 7: /* GL_QUADS */
return V_028A6C_OUTPRIM_TYPE_TRISTRIP; return V_028A6C_TRISTRIP;
default: default:
assert(0); assert(0);
return 0; return 0;
@@ -1241,18 +1241,18 @@ si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
switch (topology) { switch (topology) {
case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST: case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
return V_028A6C_OUTPRIM_TYPE_POINTLIST; return V_028A6C_POINTLIST;
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST: case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP: case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
return V_028A6C_OUTPRIM_TYPE_LINESTRIP; return V_028A6C_LINESTRIP;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST: case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP: case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN: case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
return V_028A6C_OUTPRIM_TYPE_TRISTRIP; return V_028A6C_TRISTRIP;
default: default:
assert(0); assert(0);
return 0; return 0;
@@ -1450,11 +1450,11 @@ radv_pipeline_init_input_assembly_state(struct radv_pipeline *pipeline,
pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(ia_state->topology); pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(ia_state->topology);
if (radv_pipeline_has_gs(pipeline)) { if (radv_pipeline_has_gs(pipeline)) {
if (si_conv_gl_prim_to_gs_out(gs->info.gs.output_prim) == V_028A6C_OUTPRIM_TYPE_TRISTRIP) if (si_conv_gl_prim_to_gs_out(gs->info.gs.output_prim) == V_028A6C_TRISTRIP)
pipeline->graphics.can_use_guardband = true; pipeline->graphics.can_use_guardband = true;
} else if (radv_pipeline_has_tess(pipeline)) { } else if (radv_pipeline_has_tess(pipeline)) {
if (!tes->info.tes.point_mode && if (!tes->info.tes.point_mode &&
si_conv_gl_prim_to_gs_out(tes->info.tes.primitive_mode) == V_028A6C_OUTPRIM_TYPE_TRISTRIP) si_conv_gl_prim_to_gs_out(tes->info.tes.primitive_mode) == V_028A6C_TRISTRIP)
pipeline->graphics.can_use_guardband = true; pipeline->graphics.can_use_guardband = true;
} }
@@ -3690,7 +3690,7 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2); db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2); db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE(2);
} }
if (attachment && extra) { if (attachment && extra) {
@@ -3921,8 +3921,8 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) | S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) | S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) | S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) | S_02881C_BYPASS_PRIM_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
S_02881C_BYPASS_VTX_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) | S_02881C_BYPASS_VTX_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
cull_dist_mask << 8 | cull_dist_mask << 8 |
clip_dist_mask); clip_dist_mask);
@@ -4037,8 +4037,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) | S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) | S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) | S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) | S_02881C_BYPASS_PRIM_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
S_02881C_BYPASS_VTX_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) | S_02881C_BYPASS_VTX_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
cull_dist_mask << 8 | cull_dist_mask << 8 |
clip_dist_mask); clip_dist_mask);
@@ -4079,7 +4079,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) && S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
!radv_pipeline_has_gs(pipeline)) | !radv_pipeline_has_gs(pipeline)) |
/* Reuse for NGG. */ /* Reuse for NGG. */
S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0)); S_028838_VERTEX_REUSE_DEPTH(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) | ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */ S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
@@ -4257,11 +4257,11 @@ radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
if (pipeline->device->physical_device->rad_info.has_distributed_tess) { if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI || if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10) pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS; distribution_mode = V_028B6C_TRAPEZOIDS;
else else
distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS; distribution_mode = V_028B6C_DONUTS;
} else } else
distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST; distribution_mode = V_028B6C_NO_DIST;
radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM, radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
S_028B6C_TYPE(type) | S_028B6C_TYPE(type) |
@@ -4729,7 +4729,7 @@ radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs,
gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
} else if (radv_pipeline_has_tess(pipeline)) { } else if (radv_pipeline_has_tess(pipeline)) {
if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) { if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) {
gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST; gs_out = V_028A6C_POINTLIST;
} else { } else {
gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode); gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
} }
@@ -4738,9 +4738,9 @@ radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs,
} }
if (extra && extra->use_rectlist) { if (extra && extra->use_rectlist) {
gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP; gs_out = V_028A6C_TRISTRIP;
if (radv_pipeline_has_ngg(pipeline)) if (radv_pipeline_has_ngg(pipeline))
gs_out = V_028A6C_VGT_OUT_RECT_V0; gs_out = V_028A6C_RECTLIST;
} }
radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out); radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);

2
src/amd/vulkan/radv_private.h
View File

@@ -2576,7 +2576,7 @@ si_conv_gl_prim_to_vertices(unsigned gl_prim)
case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */ case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
return 6; return 6;
case 7: /* GL_QUADS */ case 7: /* GL_QUADS */
return V_028A6C_OUTPRIM_TYPE_TRISTRIP; return V_028A6C_TRISTRIP;
default: default:
assert(0); assert(0);
return 0; return 0;

2
src/amd/vulkan/radv_shader.c
View File

@@ -896,7 +896,7 @@ static void radv_postprocess_config(const struct radv_device *device,
if (pdevice->rad_info.chip_class >= GFX10) { if (pdevice->rad_info.chip_class >= GFX10) {
vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1; vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks) | config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks) |
S_00B42C_EXCP_EN_GFX10(excp_en); S_00B42C_EXCP_EN_GFX6(excp_en);
} else { } else {
vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1; vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks) | config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks) |

2
src/amd/vulkan/si_cmd_buffer.c
View File

@@ -433,7 +433,7 @@ si_emit_graphics(struct radv_device *device,
radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0); radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
if (physical_device->rad_info.chip_class >= GFX10_3) { if (physical_device->rad_info.chip_class >= GFX10_3) {
radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, 0xff); radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);
radeon_set_context_reg(cs, 0x28848, 1 << 9); /* This fixes sample shading. */ radeon_set_context_reg(cs, 0x28848, 1 << 9); /* This fixes sample shading. */
} }

6
src/gallium/drivers/radeonsi/si_perfcounter.c
View File

@@ -836,11 +836,11 @@ static void si_pc_emit_start(struct si_context *sctx, struct si_resource *buffer
COPY_DATA_IMM, NULL, 1); COPY_DATA_IMM, NULL, 1);
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_DISABLE_AND_RESET)); S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0)); radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0));
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_START_COUNTING)); S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_START_COUNTING));
} }
/* Note: The buffer was already added in si_pc_emit_start, so we don't have to /* Note: The buffer was already added in si_pc_emit_start, so we don't have to
@@ -859,7 +859,7 @@ static void si_pc_emit_stop(struct si_context *sctx, struct si_resource *buffer,
radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0)); radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0));
radeon_set_uconfig_reg( radeon_set_uconfig_reg(
cs, R_036020_CP_PERFMON_CNTL, cs, R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_STOP_COUNTING) | S_036020_PERFMON_SAMPLE_ENABLE(1)); S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_STOP_COUNTING) | S_036020_PERFMON_SAMPLE_ENABLE(1));
} }
static void si_pc_emit_read(struct si_context *sctx, struct si_pc_block *block, unsigned count, static void si_pc_emit_read(struct si_context *sctx, struct si_pc_block *block, unsigned count,

4
src/gallium/drivers/radeonsi/si_pipe.c
View File

@@ -1128,8 +1128,8 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
} else if (sscreen->info.chip_class >= GFX7) { } else if (sscreen->info.chip_class >= GFX7) {
if (sscreen->info.chip_class >= GFX8) if (sscreen->info.chip_class >= GFX8)
--max_offchip_buffers; --max_offchip_buffers;
sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) | sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) |
S_03093C_OFFCHIP_GRANULARITY(offchip_granularity); S_03093C_OFFCHIP_GRANULARITY_GFX7(offchip_granularity);
} else { } else {
assert(offchip_granularity == V_03093C_X_8K_DWORDS); assert(offchip_granularity == V_03093C_X_8K_DWORDS);
sscreen->vgt_hs_offchip_param = S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); sscreen->vgt_hs_offchip_param = S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);

56
src/gallium/drivers/radeonsi/si_state.c
View File

@@ -757,8 +757,8 @@ static void si_emit_clip_regs(struct si_context *sctx)
unsigned initial_cdw = sctx->gfx_cs->current.cdw; unsigned initial_cdw = sctx->gfx_cs->current.cdw;
unsigned pa_cl_cntl = S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) | unsigned pa_cl_cntl = S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) | S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
S_02881C_BYPASS_VTX_RATE_COMBINER_GFX103(sctx->chip_class >= GFX10_3) | S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->chip_class >= GFX10_3) |
S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(sctx->chip_class >= GFX10_3) | S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->chip_class >= GFX10_3) |
clipdist_mask | (culldist_mask << 8); clipdist_mask | (culldist_mask << 8);
if (sctx->chip_class >= GFX10) { if (sctx->chip_class >= GFX10) {
@@ -1387,7 +1387,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) | S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) | S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) | S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
S_028010_CENTROID_COMPUTATION_MODE_GFX103(sctx->chip_class >= GFX10_3 ? 2 : 0)); S_028010_CENTROID_COMPUTATION_MODE(sctx->chip_class >= GFX10_3 ? 2 : 0));
db_shader_control = sctx->ps_db_shader_control; db_shader_control = sctx->ps_db_shader_control;
@@ -2883,8 +2883,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */ meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */ meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
} else { } else {
meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */ meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */ meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */
} }
/* Colorbuffers. */ /* Colorbuffers. */
@@ -3152,12 +3152,12 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */ radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */ radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
radeon_emit(cs, /* DB_RMI_L2_CACHE_CONTROL */ radeon_emit(cs, /* DB_RMI_L2_CACHE_CONTROL */
S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) | S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) | S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_HTILE_WR_POLICY(meta_write_policy) | S_02807C_HTILE_WR_POLICY(meta_write_policy) |
S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) | S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) | S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) |
S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) | S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) |
S_02807C_HTILE_RD_POLICY(meta_read_policy) | S_02807C_HTILE_RD_POLICY(meta_read_policy) |
S_02807C_Z_BIG_PAGE(zs_big_page) | S_02807C_Z_BIG_PAGE(zs_big_page) |
S_02807C_S_BIG_PAGE(zs_big_page)); S_02807C_S_BIG_PAGE(zs_big_page));
@@ -3254,11 +3254,11 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
S_028410_CMASK_WR_POLICY(meta_write_policy) | S_028410_CMASK_WR_POLICY(meta_write_policy) |
S_028410_FMASK_WR_POLICY(meta_write_policy) | S_028410_FMASK_WR_POLICY(meta_write_policy) |
S_028410_DCC_WR_POLICY(meta_write_policy) | S_028410_DCC_WR_POLICY(meta_write_policy) |
S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) | S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM) |
S_028410_CMASK_RD_POLICY(meta_read_policy) | S_028410_CMASK_RD_POLICY(meta_read_policy) |
S_028410_FMASK_RD_POLICY(meta_read_policy) | S_028410_FMASK_RD_POLICY(meta_read_policy) |
S_028410_DCC_RD_POLICY(meta_read_policy) | S_028410_DCC_RD_POLICY(meta_read_policy) |
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD) | S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA) |
S_028410_FMASK_BIG_PAGE(color_big_page) | S_028410_FMASK_BIG_PAGE(color_big_page) |
S_028410_COLOR_BIG_PAGE(color_big_page)); S_028410_COLOR_BIG_PAGE(color_big_page));
} }
@@ -3489,7 +3489,7 @@ static void si_emit_msaa_config(struct si_context *sctx)
sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) | sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) | S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) |
S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(sctx->chip_class >= GFX10_3); S_028BE0_COVERED_CENTROID_IS_CENTER(sctx->chip_class >= GFX10_3);
if (sctx->framebuffer.nr_samples > 1) { if (sctx->framebuffer.nr_samples > 1) {
db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) | db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
@@ -4043,43 +4043,43 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu
data_format = V_008F14_IMG_DATA_FORMAT_FMASK; data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
switch (FMASK(res->nr_samples, res->nr_storage_samples)) { switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
case FMASK(2, 1): case FMASK(2, 1):
num_format = V_008F14_IMG_FMASK_8_2_1; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_1;
break; break;
case FMASK(2, 2): case FMASK(2, 2):
num_format = V_008F14_IMG_FMASK_8_2_2; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_2;
break; break;
case FMASK(4, 1): case FMASK(4, 1):
num_format = V_008F14_IMG_FMASK_8_4_1; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_1;
break; break;
case FMASK(4, 2): case FMASK(4, 2):
num_format = V_008F14_IMG_FMASK_8_4_2; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_2;
break; break;
case FMASK(4, 4): case FMASK(4, 4):
num_format = V_008F14_IMG_FMASK_8_4_4; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_4;
break; break;
case FMASK(8, 1): case FMASK(8, 1):
num_format = V_008F14_IMG_FMASK_8_8_1; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_8_1;
break; break;
case FMASK(8, 2): case FMASK(8, 2):
num_format = V_008F14_IMG_FMASK_16_8_2; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_16_8_2;
break; break;
case FMASK(8, 4): case FMASK(8, 4):
num_format = V_008F14_IMG_FMASK_32_8_4; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_8_4;
break; break;
case FMASK(8, 8): case FMASK(8, 8):
num_format = V_008F14_IMG_FMASK_32_8_8; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_8_8;
break; break;
case FMASK(16, 1): case FMASK(16, 1):
num_format = V_008F14_IMG_FMASK_16_16_1; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_16_16_1;
break; break;
case FMASK(16, 2): case FMASK(16, 2):
num_format = V_008F14_IMG_FMASK_32_16_2; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_16_2;
break; break;
case FMASK(16, 4): case FMASK(16, 4):
num_format = V_008F14_IMG_FMASK_64_16_4; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_64_16_4;
break; break;
case FMASK(16, 8): case FMASK(16, 8):
num_format = V_008F14_IMG_FMASK_64_16_8; num_format = V_008F14_IMG_NUM_FORMAT_FMASK_64_16_8;
break; break;
default: default:
unreachable("invalid nr_samples"); unreachable("invalid nr_samples");
@@ -4461,7 +4461,7 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
} else { } else {
rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) | rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
S_008F38_FILTER_PREC_FIX(1) | S_008F38_FILTER_PREC_FIX(1) |
S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8); S_008F38_ANISO_OVERRIDE_GFX8(sctx->chip_class >= GFX8);
} }
/* Create sampler resource for integer textures. */ /* Create sampler resource for integer textures. */
@@ -5347,7 +5347,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
} }
if (sctx->chip_class >= GFX10_3) { if (sctx->chip_class >= GFX10_3) {
si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, 0xff); si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);
si_pm4_set_reg(pm4, 0x28848, 1 << 9); /* This fixes sample shading. */ si_pm4_set_reg(pm4, 0x28848, 1 << 9); /* This fixes sample shading. */
} }

32
src/gallium/drivers/radeonsi/si_state_draw.c
View File

@@ -527,22 +527,22 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
static unsigned si_conv_prim_to_gs_out(unsigned mode) static unsigned si_conv_prim_to_gs_out(unsigned mode)
{ {
static const int prim_conv[] = { static const int prim_conv[] = {
[PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST, [PIPE_PRIM_POINTS] = V_028A6C_POINTLIST,
[PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, [PIPE_PRIM_LINES] = V_028A6C_LINESTRIP,
[PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, [PIPE_PRIM_LINE_LOOP] = V_028A6C_LINESTRIP,
[PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, [PIPE_PRIM_LINE_STRIP] = V_028A6C_LINESTRIP,
[PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, [PIPE_PRIM_TRIANGLES] = V_028A6C_TRISTRIP,
[PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_TRISTRIP,
[PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_TRISTRIP,
[PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, [PIPE_PRIM_QUADS] = V_028A6C_TRISTRIP,
[PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, [PIPE_PRIM_QUAD_STRIP] = V_028A6C_TRISTRIP,
[PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, [PIPE_PRIM_POLYGON] = V_028A6C_TRISTRIP,
[PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_LINESTRIP,
[PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_LINESTRIP,
[PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_TRISTRIP,
[PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_TRISTRIP,
[PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST, [PIPE_PRIM_PATCHES] = V_028A6C_POINTLIST,
[SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0, [SI_PRIM_RECTANGLE_LIST] = V_028A6C_RECTLIST,
}; };
assert(mode < ARRAY_SIZE(prim_conv)); assert(mode < ARRAY_SIZE(prim_conv));

8
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@@ -359,11 +359,11 @@ static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shad
if (sscreen->info.has_distributed_tess) { if (sscreen->info.has_distributed_tess) {
if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10) if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10)
distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS; distribution_mode = V_028B6C_TRAPEZOIDS;
else else
distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS; distribution_mode = V_028B6C_DONUTS;
} else } else
distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST; distribution_mode = V_028B6C_NO_DIST;
assert(pm4->shader); assert(pm4->shader);
pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) | pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
@@ -1215,7 +1215,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
shader->ctx_reg.ngg.pa_cl_ngg_cntl = shader->ctx_reg.ngg.pa_cl_ngg_cntl =
S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX) | S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX) |
/* Reuse for NGG. */ /* Reuse for NGG. */
S_028838_VERTEX_REUSE_DEPTH_GFX103(sscreen->info.chip_class >= GFX10_3 ? 30 : 0); S_028838_VERTEX_REUSE_DEPTH(sscreen->info.chip_class >= GFX10_3 ? 30 : 0);
shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true); shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
/* Oversubscribe PC. This improves performance when there are too many varyings. */ /* Oversubscribe PC. This improves performance when there are too many varyings. */