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intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.

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This patch modifies intel_region_get_aligned_offset() to make the
appropriate calculation when the blorp engine sets up a W-tiled
stencil buffer using a Y-tiled SURFACE_STATE.

NOTE: This is a candidate for stable release branches.

Acked-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Paul Berry
2012-08-30 11:16:44 -07:00
parent 50dec7fc2d
commit b760c9913d
8 changed files with 31 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mesa/drivers/dri/i965/brw_blorp.cpp
View File

@@ -129,7 +129,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
*tile_y = y_offset & mask_y;
return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
y_offset & ~mask_y);
y_offset & ~mask_y,
map_stencil_as_y_tiled);
}

5
src/mesa/drivers/dri/i965/brw_misc_state.c
View File

@@ -474,7 +474,7 @@ static void emit_depthbuffer(struct brw_context *brw)
offset = intel_region_get_aligned_offset(region,
draw_x & ~tile_mask_x,
draw_y & ~tile_mask_y);
draw_y & ~tile_mask_y, false);
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
@@ -518,7 +518,8 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_region,
draw_x & ~tile_mask_x,
(draw_y & ~tile_mask_y) / 2);
(draw_y & ~tile_mask_y) / 2,
false);
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));

4
src/mesa/drivers/dri/i965/gen6_blorp.cpp
View File

@@ -843,7 +843,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t offset =
intel_region_get_aligned_offset(params->depth.mt->region,
draw_x & ~tile_mask_x,
draw_y & ~tile_mask_y);
draw_y & ~tile_mask_y, false);
/* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
* (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
@@ -896,7 +896,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_region,
draw_x & ~tile_mask_x,
(draw_y & ~tile_mask_y) / 2);
(draw_y & ~tile_mask_y) / 2, false);
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));

4
src/mesa/drivers/dri/i965/gen7_blorp.cpp
View File

@@ -591,7 +591,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t offset =
intel_region_get_aligned_offset(params->depth.mt->region,
draw_x & ~tile_mask_x,
draw_y & ~tile_mask_y);
draw_y & ~tile_mask_y, false);
/* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
* (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
@@ -640,7 +640,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_region,
draw_x & ~tile_mask_x,
(draw_y & ~tile_mask_y) / 2);
(draw_y & ~tile_mask_y) / 2, false);
BEGIN_BATCH(3);
OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));

6
src/mesa/drivers/dri/i965/gen7_misc_state.c
View File

@@ -181,7 +181,8 @@ static void emit_depthbuffer(struct brw_context *brw)
offset = intel_region_get_aligned_offset(region,
draw_x & ~tile_mask_x,
draw_y & ~tile_mask_y);
draw_y & ~tile_mask_y,
false);
assert(region->tiling == I915_TILING_Y);
@@ -215,7 +216,8 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_mt->region,
draw_x & ~tile_mask_x,
(draw_y & ~tile_mask_y) / 2);
(draw_y & ~tile_mask_y) / 2,
false);
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH(hiz_mt->region->pitch * hiz_mt->region->cpp - 1);

2
src/mesa/drivers/dri/intel/intel_fbo.c
View File

@@ -586,7 +586,7 @@ intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb,
*tile_x = irb->draw_x & mask_x;
*tile_y = irb->draw_y & mask_y;
return intel_region_get_aligned_offset(region, irb->draw_x & ~mask_x,
irb->draw_y & ~mask_y);
irb->draw_y & ~mask_y, false);
}
/**

18
src/mesa/drivers/dri/intel/intel_regions.c
View File

@@ -437,12 +437,26 @@ intel_region_get_tile_masks(struct intel_region *region,
*/
uint32_t
intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
uint32_t y)
uint32_t y, bool map_stencil_as_y_tiled)
{
int cpp = region->cpp;
uint32_t pitch = region->pitch * cpp;
uint32_t tiling = region->tiling;
switch (region->tiling) {
if (map_stencil_as_y_tiled) {
tiling = I915_TILING_Y;
/* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
* gets transformed into a 32-high Y-tile. Accordingly, the pitch of
* the resulting region is twice the pitch of the original region, since
* each row in the Y-tiled view corresponds to two rows in the actual
* W-tiled surface. So we need to correct the pitch before computing
* the offsets.
*/
pitch *= 2;
}
switch (tiling) {
default:
assert(false);
case I915_TILING_NONE:

2
src/mesa/drivers/dri/intel/intel_regions.h
View File

@@ -140,7 +140,7 @@ intel_region_get_tile_masks(struct intel_region *region,
uint32_t
intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
uint32_t y);
uint32_t y, bool map_stencil_as_y_tiled);
/**
* Used with images created with image_from_names