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tgsi/ureg: don't emit in/out arrays if drivers don't support ranged declarations

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Softpipe, llvmpipe, r300g, and radeonsi pass tests. Other drivers need testing.

Freedreno and nv30 are definitely broken. Other drivers seem to be alright.
This commit is contained in:
Marek Olšák
2015-05-25 19:30:44 +02:00
parent a015b3952f
commit b6ebe7eabf
17 changed files with 162 additions and 40 deletions
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1
src/gallium/auxiliary/gallivm/lp_bld_limits.h
View File

@@ -125,6 +125,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 1;
case PIPE_SHADER_CAP_DOUBLES:
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:

1
src/gallium/auxiliary/tgsi/tgsi_exec.h
View File

@@ -458,6 +458,7 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
return 1;
case PIPE_SHADER_CAP_DOUBLES:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 1;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:

172
src/gallium/auxiliary/tgsi/tgsi_ureg.c
View File

@@ -26,6 +26,7 @@
**************************************************************************/
#include "pipe/p_screen.h"
#include "pipe/p_context.h"
#include "pipe/p_state.h"
#include "tgsi/tgsi_ureg.h"
@@ -96,7 +97,7 @@ struct const_decl {
struct ureg_program
{
unsigned processor;
struct pipe_context *pipe;
bool supports_any_inout_decl_range;
struct {
unsigned semantic_name;
@@ -906,7 +907,11 @@ ureg_emit_src( struct ureg_program *ureg,
out[n].ind.File = src.IndirectFile;
out[n].ind.Swizzle = src.IndirectSwizzle;
out[n].ind.Index = src.IndirectIndex;
out[n].ind.ArrayID = src.ArrayID;
if (!ureg->supports_any_inout_decl_range &&
(src.File == TGSI_FILE_INPUT || src.File == TGSI_FILE_OUTPUT))
out[n].ind.ArrayID = 0;
else
out[n].ind.ArrayID = src.ArrayID;
n++;
}
@@ -922,7 +927,11 @@ ureg_emit_src( struct ureg_program *ureg,
out[n].ind.File = src.DimIndFile;
out[n].ind.Swizzle = src.DimIndSwizzle;
out[n].ind.Index = src.DimIndIndex;
out[n].ind.ArrayID = src.ArrayID;
if (!ureg->supports_any_inout_decl_range &&
(src.File == TGSI_FILE_INPUT || src.File == TGSI_FILE_OUTPUT))
out[n].ind.ArrayID = 0;
else
out[n].ind.ArrayID = src.ArrayID;
} else {
out[n].dim.Indirect = 0;
out[n].dim.Index = src.DimensionIndex;
@@ -964,7 +973,11 @@ ureg_emit_dst( struct ureg_program *ureg,
out[n].ind.File = dst.IndirectFile;
out[n].ind.Swizzle = dst.IndirectSwizzle;
out[n].ind.Index = dst.IndirectIndex;
out[n].ind.ArrayID = dst.ArrayID;
if (!ureg->supports_any_inout_decl_range &&
(dst.File == TGSI_FILE_INPUT || dst.File == TGSI_FILE_OUTPUT))
out[n].ind.ArrayID = 0;
else
out[n].ind.ArrayID = dst.ArrayID;
n++;
}
@@ -980,7 +993,11 @@ ureg_emit_dst( struct ureg_program *ureg,
out[n].ind.File = dst.DimIndFile;
out[n].ind.Swizzle = dst.DimIndSwizzle;
out[n].ind.Index = dst.DimIndIndex;
out[n].ind.ArrayID = dst.ArrayID;
if (!ureg->supports_any_inout_decl_range &&
(dst.File == TGSI_FILE_INPUT || dst.File == TGSI_FILE_OUTPUT))
out[n].ind.ArrayID = 0;
else
out[n].ind.ArrayID = dst.ArrayID;
} else {
out[n].dim.Indirect = 0;
out[n].dim.Index = dst.DimensionIndex;
@@ -1489,7 +1506,7 @@ emit_property(struct ureg_program *ureg,
static void emit_decls( struct ureg_program *ureg )
{
unsigned i;
unsigned i,j;
for (i = 0; i < Elements(ureg->properties); i++)
if (ureg->properties[i] != ~0)
@@ -1502,28 +1519,60 @@ static void emit_decls( struct ureg_program *ureg )
}
}
} else if (ureg->processor == TGSI_PROCESSOR_FRAGMENT) {
for (i = 0; i < ureg->nr_inputs; i++) {
emit_decl_fs(ureg,
TGSI_FILE_INPUT,
ureg->input[i].first,
ureg->input[i].last,
ureg->input[i].semantic_name,
ureg->input[i].semantic_index,
ureg->input[i].interp,
ureg->input[i].cylindrical_wrap,
ureg->input[i].interp_location,
ureg->input[i].array_id);
if (ureg->supports_any_inout_decl_range) {
for (i = 0; i < ureg->nr_inputs; i++) {
emit_decl_fs(ureg,
TGSI_FILE_INPUT,
ureg->input[i].first,
ureg->input[i].last,
ureg->input[i].semantic_name,
ureg->input[i].semantic_index,
ureg->input[i].interp,
ureg->input[i].cylindrical_wrap,
ureg->input[i].interp_location,
ureg->input[i].array_id);
}
}
else {
for (i = 0; i < ureg->nr_inputs; i++) {
for (j = ureg->input[i].first; j <= ureg->input[i].last; j++) {
emit_decl_fs(ureg,
TGSI_FILE_INPUT,
j, j,
ureg->input[i].semantic_name,
ureg->input[i].semantic_index +
(j - ureg->input[i].first),
ureg->input[i].interp,
ureg->input[i].cylindrical_wrap,
ureg->input[i].interp_location, 0);
}
}
}
} else {
for (i = 0; i < ureg->nr_inputs; i++) {
emit_decl_semantic(ureg,
TGSI_FILE_INPUT,
ureg->input[i].first,
ureg->input[i].last,
ureg->input[i].semantic_name,
ureg->input[i].semantic_index,
TGSI_WRITEMASK_XYZW,
ureg->input[i].array_id);
if (ureg->supports_any_inout_decl_range) {
for (i = 0; i < ureg->nr_inputs; i++) {
emit_decl_semantic(ureg,
TGSI_FILE_INPUT,
ureg->input[i].first,
ureg->input[i].last,
ureg->input[i].semantic_name,
ureg->input[i].semantic_index,
TGSI_WRITEMASK_XYZW,
ureg->input[i].array_id);
}
}
else {
for (i = 0; i < ureg->nr_inputs; i++) {
for (j = ureg->input[i].first; j <= ureg->input[i].last; j++) {
emit_decl_semantic(ureg,
TGSI_FILE_INPUT,
j, j,
ureg->input[i].semantic_name,
ureg->input[i].semantic_index +
(j - ureg->input[i].first),
TGSI_WRITEMASK_XYZW, 0);
}
}
}
}
@@ -1537,15 +1586,30 @@ static void emit_decls( struct ureg_program *ureg )
TGSI_WRITEMASK_XYZW, 0);
}
for (i = 0; i < ureg->nr_outputs; i++) {
emit_decl_semantic(ureg,
TGSI_FILE_OUTPUT,
ureg->output[i].first,
ureg->output[i].last,
ureg->output[i].semantic_name,
ureg->output[i].semantic_index,
ureg->output[i].usage_mask,
ureg->output[i].array_id);
if (ureg->supports_any_inout_decl_range) {
for (i = 0; i < ureg->nr_outputs; i++) {
emit_decl_semantic(ureg,
TGSI_FILE_OUTPUT,
ureg->output[i].first,
ureg->output[i].last,
ureg->output[i].semantic_name,
ureg->output[i].semantic_index,
ureg->output[i].usage_mask,
ureg->output[i].array_id);
}
}
else {
for (i = 0; i < ureg->nr_outputs; i++) {
for (j = ureg->output[i].first; j <= ureg->output[i].last; j++) {
emit_decl_semantic(ureg,
TGSI_FILE_OUTPUT,
j, j,
ureg->output[i].semantic_name,
ureg->output[i].semantic_index +
(j - ureg->output[i].first),
ureg->output[i].usage_mask, 0);
}
}
}
for (i = 0; i < ureg->nr_samplers; i++) {
@@ -1759,7 +1823,38 @@ void ureg_free_tokens( const struct tgsi_token *tokens )
}
struct ureg_program *ureg_create( unsigned processor )
static INLINE unsigned
pipe_shader_from_tgsi_processor(unsigned processor)
{
switch (processor) {
case TGSI_PROCESSOR_VERTEX:
return PIPE_SHADER_VERTEX;
case TGSI_PROCESSOR_TESS_CTRL:
return PIPE_SHADER_TESS_CTRL;
case TGSI_PROCESSOR_TESS_EVAL:
return PIPE_SHADER_TESS_EVAL;
case TGSI_PROCESSOR_GEOMETRY:
return PIPE_SHADER_GEOMETRY;
case TGSI_PROCESSOR_FRAGMENT:
return PIPE_SHADER_FRAGMENT;
case TGSI_PROCESSOR_COMPUTE:
return PIPE_SHADER_COMPUTE;
default:
assert(0);
return PIPE_SHADER_VERTEX;
}
}
struct ureg_program *
ureg_create(unsigned processor)
{
return ureg_create_with_screen(processor, NULL);
}
struct ureg_program *
ureg_create_with_screen(unsigned processor, struct pipe_screen *screen)
{
int i;
struct ureg_program *ureg = CALLOC_STRUCT( ureg_program );
@@ -1767,6 +1862,11 @@ struct ureg_program *ureg_create( unsigned processor )
goto no_ureg;
ureg->processor = processor;
ureg->supports_any_inout_decl_range =
screen &&
screen->get_shader_param(screen,
pipe_shader_from_tgsi_processor(processor),
PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE) != 0;
for (i = 0; i < Elements(ureg->properties); i++)
ureg->properties[i] = ~0;

6
src/gallium/auxiliary/tgsi/tgsi_ureg.h
View File

@@ -36,6 +36,7 @@
extern "C" {
#endif
struct pipe_screen;
struct ureg_program;
struct pipe_stream_output_info;
@@ -98,7 +99,10 @@ struct ureg_dst
struct pipe_context;
struct ureg_program *
ureg_create( unsigned processor );
ureg_create(unsigned processor);
struct ureg_program *
ureg_create_with_screen(unsigned processor, struct pipe_screen *screen);
const struct tgsi_token *
ureg_finalize( struct ureg_program * );

2
src/gallium/docs/source/screen.rst
View File

@@ -340,6 +340,8 @@ to be 0.
DLDEXP are supported.
* ``PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED``: Whether FMA and DFMA (doubles only)
are supported.
* ``PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE``: Whether the driver doesn't
ignore tgsi_declaration_range::Last for shader inputs and outputs.
.. _pipe_compute_cap:

1
src/gallium/drivers/freedreno/freedreno_screen.c
View File

@@ -375,6 +375,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;

1
src/gallium/drivers/i915/i915_screen.c
View File

@@ -165,6 +165,7 @@ i915_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_sha
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
default:
debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);

2
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View File

@@ -252,6 +252,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
default:
debug_printf("unknown vertex shader param %d\n", param);
@@ -292,6 +293,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
default:
debug_printf("unknown fragment shader param %d\n", param);

1
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View File

@@ -291,6 +291,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
default:
NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);

1
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View File

@@ -297,6 +297,7 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
return 1;
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
return 16; /* would be 32 in linked (OpenGL-style) mode */

2
src/gallium/drivers/r300/r300_screen.c
View File

@@ -274,6 +274,7 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, e
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return (is_r500 ? 256 : 32) * sizeof(float[4]);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return is_r500 ? 128 : is_r400 ? 64 : 32;
@@ -333,6 +334,7 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, e
case PIPE_SHADER_CAP_MAX_PREDS:
return 0; /* unused */
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 1;
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:

1
src/gallium/drivers/r600/r600_pipe.c
View File

@@ -495,6 +495,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
}
return 0;

1
src/gallium/drivers/radeonsi/si_pipe.c
View File

@@ -452,6 +452,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 1;
}
return 0;

2
src/gallium/drivers/svga/svga_screen.c
View File

@@ -377,6 +377,7 @@ static int svga_get_shader_param(struct pipe_screen *screen, unsigned shader, en
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
}
/* If we get here, we failed to handle a cap above */
@@ -434,6 +435,7 @@ static int svga_get_shader_param(struct pipe_screen *screen, unsigned shader, en
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
}
/* If we get here, we failed to handle a cap above */

1
src/gallium/drivers/vc4/vc4_screen.c
View File

@@ -323,6 +323,7 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:

1
src/gallium/include/pipe/p_defines.h
View File

@@ -669,6 +669,7 @@ enum pipe_shader_cap
PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */
PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED,
PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED,
PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
};
/**

6
src/mesa/state_tracker/st_program.c
View File

@@ -321,7 +321,7 @@ st_translate_vertex_program(struct st_context *st,
_mesa_remove_output_reads(&stvp->Base.Base, PROGRAM_OUTPUT);
}
ureg = ureg_create( TGSI_PROCESSOR_VERTEX );
ureg = ureg_create_with_screen(TGSI_PROCESSOR_VERTEX, st->pipe->screen);
if (ureg == NULL) {
free(vpv);
return NULL;
@@ -732,7 +732,7 @@ st_translate_fragment_program(struct st_context *st,
}
}
ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT );
ureg = ureg_create_with_screen(TGSI_PROCESSOR_FRAGMENT, st->pipe->screen);
if (ureg == NULL) {
free(variant);
return NULL;
@@ -890,7 +890,7 @@ st_translate_geometry_program(struct st_context *st,
if (!gpv)
return NULL;
ureg = ureg_create(TGSI_PROCESSOR_GEOMETRY);
ureg = ureg_create_with_screen(TGSI_PROCESSOR_GEOMETRY, st->pipe->screen);
if (ureg == NULL) {
free(gpv);
return NULL;