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radv: do not recursively begin/end render pass for meta operations

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To avoid breaking SQTT user markers that are emitted to report
barriers and layout transitions to RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4136>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4136>
This commit is contained in:
Samuel Pitoiset
2020-03-10 18:35:15 +01:00
committed by Marge Bot
parent c78e88e8a6
commit b6cebf6439
9 changed files with 180 additions and 150 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -4398,12 +4398,10 @@ radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
} }
} }
void radv_CmdBeginRenderPass( void
VkCommandBuffer commandBuffer, radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
const VkRenderPassBeginInfo* pRenderPassBegin, const VkRenderPassBeginInfo *pRenderPassBegin)
VkSubpassContents contents)
{ {
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass); RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer); RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
VkResult result; VkResult result;
@@ -4419,6 +4417,16 @@ void radv_CmdBeginRenderPass(
result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin); result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
if (result != VK_SUCCESS) if (result != VK_SUCCESS)
return; return;
}
void radv_CmdBeginRenderPass(
VkCommandBuffer commandBuffer,
const VkRenderPassBeginInfo* pRenderPassBegin,
VkSubpassContents contents)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
radv_cmd_buffer_begin_subpass(cmd_buffer, 0); radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
} }
@@ -5270,6 +5278,19 @@ void radv_unaligned_dispatch(
radv_dispatch(cmd_buffer, &info); radv_dispatch(cmd_buffer, &info);
} }
void
radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
{
vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
cmd_buffer->state.pass = NULL;
cmd_buffer->state.subpass = NULL;
cmd_buffer->state.attachments = NULL;
cmd_buffer->state.framebuffer = NULL;
cmd_buffer->state.subpass_sample_locs = NULL;
}
void radv_CmdEndRenderPass( void radv_CmdEndRenderPass(
VkCommandBuffer commandBuffer) VkCommandBuffer commandBuffer)
{ {
@@ -5279,14 +5300,7 @@ void radv_CmdEndRenderPass(
radv_cmd_buffer_end_subpass(cmd_buffer); radv_cmd_buffer_end_subpass(cmd_buffer);
vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments); radv_cmd_buffer_end_render_pass(cmd_buffer);
vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
cmd_buffer->state.pass = NULL;
cmd_buffer->state.subpass = NULL;
cmd_buffer->state.attachments = NULL;
cmd_buffer->state.framebuffer = NULL;
cmd_buffer->state.subpass_sample_locs = NULL;
} }
void radv_CmdEndRenderPass2( void radv_CmdEndRenderPass2(

17
src/amd/vulkan/radv_meta_blit.c
View File

@@ -350,7 +350,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout); unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout);
fs_key = radv_format_meta_fs_key(dest_image->vk_format); fs_key = radv_format_meta_fs_key(dest_image->vk_format);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit.render_pass[fs_key][dst_layout], .renderPass = device->meta_state.blit.render_pass[fs_key][dst_layout],
@@ -361,7 +361,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, VK_SUBPASS_CONTENTS_INLINE); });
switch (src_image->type) { switch (src_image->type) {
case VK_IMAGE_TYPE_1D: case VK_IMAGE_TYPE_1D:
pipeline = &device->meta_state.blit.pipeline_1d_src[fs_key]; pipeline = &device->meta_state.blit.pipeline_1d_src[fs_key];
@@ -379,7 +379,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
} }
case VK_IMAGE_ASPECT_DEPTH_BIT: { case VK_IMAGE_ASPECT_DEPTH_BIT: {
enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout); enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit.depth_only_rp[ds_layout], .renderPass = device->meta_state.blit.depth_only_rp[ds_layout],
@@ -390,7 +390,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, VK_SUBPASS_CONTENTS_INLINE); });
switch (src_image->type) { switch (src_image->type) {
case VK_IMAGE_TYPE_1D: case VK_IMAGE_TYPE_1D:
pipeline = &device->meta_state.blit.depth_only_1d_pipeline; pipeline = &device->meta_state.blit.depth_only_1d_pipeline;
@@ -408,7 +408,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
} }
case VK_IMAGE_ASPECT_STENCIL_BIT: { case VK_IMAGE_ASPECT_STENCIL_BIT: {
enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout); enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit.stencil_only_rp[ds_layout], .renderPass = device->meta_state.blit.stencil_only_rp[ds_layout],
@@ -419,7 +419,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, VK_SUBPASS_CONTENTS_INLINE); });
switch (src_image->type) { switch (src_image->type) {
case VK_IMAGE_TYPE_1D: case VK_IMAGE_TYPE_1D:
pipeline = &device->meta_state.blit.stencil_only_1d_pipeline; pipeline = &device->meta_state.blit.stencil_only_1d_pipeline;
@@ -439,6 +439,9 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
unreachable("bad VkImageType"); unreachable("bad VkImageType");
} }
radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]);
if (!*pipeline) { if (!*pipeline) {
VkResult ret = build_pipeline(device, src_iview->aspect_mask, translate_sampler_dim(src_image->type), fs_key, pipeline); VkResult ret = build_pipeline(device, src_iview->aspect_mask, translate_sampler_dim(src_image->type), fs_key, pipeline);
if (ret != VK_SUCCESS) { if (ret != VK_SUCCESS) {
@@ -491,7 +494,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0); radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
fail_pipeline: fail_pipeline:
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer)); radv_cmd_buffer_end_render_pass(cmd_buffer);
/* At the point where we emit the draw call, all data from the /* At the point where we emit the draw call, all data from the
* descriptor sets, etc. has been used. We are free to delete it. * descriptor sets, etc. has been used. We are free to delete it.

20
src/amd/vulkan/radv_meta_blit2d.c
View File

@@ -299,7 +299,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
} }
} }
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit2d_render_passes[fs_key][dst_layout], .renderPass = device->meta_state.blit2d_render_passes[fs_key][dst_layout],
@@ -310,8 +310,10 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, VK_SUBPASS_CONTENTS_INLINE); });
radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]);
bind_pipeline(cmd_buffer, src_type, fs_key, log2_samples); bind_pipeline(cmd_buffer, src_type, fs_key, log2_samples);
} else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) { } else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
@@ -325,7 +327,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
} }
} }
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit2d_depth_only_rp[ds_layout], .renderPass = device->meta_state.blit2d_depth_only_rp[ds_layout],
@@ -336,8 +338,10 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, VK_SUBPASS_CONTENTS_INLINE); });
radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]);
bind_depth_pipeline(cmd_buffer, src_type, log2_samples); bind_depth_pipeline(cmd_buffer, src_type, log2_samples);
@@ -352,7 +356,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
} }
} }
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit2d_stencil_only_rp[ds_layout], .renderPass = device->meta_state.blit2d_stencil_only_rp[ds_layout],
@@ -363,8 +367,10 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, VK_SUBPASS_CONTENTS_INLINE); });
radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]);
bind_stencil_pipeline(cmd_buffer, src_type, log2_samples); bind_stencil_pipeline(cmd_buffer, src_type, log2_samples);
} else } else
@@ -387,7 +393,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0); radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer)); radv_cmd_buffer_end_render_pass(cmd_buffer);
fail_pipeline: fail_pipeline:
/* At the point where we emit the draw call, all data from the /* At the point where we emit the draw call, all data from the

10
src/amd/vulkan/radv_meta_clear.c
View File

@@ -2153,7 +2153,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
&cmd_buffer->pool->alloc, &cmd_buffer->pool->alloc,
&pass); &pass);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderArea = { .renderArea = {
@@ -2167,8 +2167,10 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
.framebuffer = fb, .framebuffer = fb,
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, });
VK_SUBPASS_CONTENTS_INLINE);
radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]);
VkClearAttachment clear_att = { VkClearAttachment clear_att = {
.aspectMask = range->aspectMask, .aspectMask = range->aspectMask,
@@ -2187,7 +2189,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false); emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false);
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer)); radv_cmd_buffer_end_render_pass(cmd_buffer);
radv_DestroyRenderPass(device_h, pass, radv_DestroyRenderPass(device_h, pass,
&cmd_buffer->pool->alloc); &cmd_buffer->pool->alloc);
radv_DestroyFramebuffer(device_h, fb, radv_DestroyFramebuffer(device_h, fb,

9
src/amd/vulkan/radv_meta_decompress.c
View File

@@ -454,7 +454,7 @@ radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer,
.layers = 1 .layers = 1
}, &cmd_buffer->pool->alloc, &fb_h); }, &cmd_buffer->pool->alloc, &fb_h);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = state->depth_decomp[samples_log2].pass, .renderPass = state->depth_decomp[samples_log2].pass,
@@ -471,11 +471,12 @@ radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer,
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, });
VK_SUBPASS_CONTENTS_INLINE); radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]);
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0); radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer)); radv_cmd_buffer_end_render_pass(cmd_buffer);
radv_DestroyFramebuffer(radv_device_to_handle(device), fb_h, radv_DestroyFramebuffer(radv_device_to_handle(device), fb_h,
&cmd_buffer->pool->alloc); &cmd_buffer->pool->alloc);

19
src/amd/vulkan/radv_meta_fast_clear.c
View File

@@ -626,31 +626,28 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer,
.layers = 1 .layers = 1
}, &cmd_buffer->pool->alloc, &fb_h); }, &cmd_buffer->pool->alloc, &fb_h);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.fast_clear_flush.pass, .renderPass = device->meta_state.fast_clear_flush.pass,
.framebuffer = fb_h, .framebuffer = fb_h,
.renderArea = { .renderArea = {
.offset = { .offset = { 0, 0, },
0, .extent = { width, height, }
0,
},
.extent = {
width,
height,
}
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, VK_SUBPASS_CONTENTS_INLINE); });
radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]);
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0); radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer)); radv_cmd_buffer_end_render_pass(cmd_buffer);
radv_DestroyFramebuffer(radv_device_to_handle(device), fb_h, radv_DestroyFramebuffer(radv_device_to_handle(device), fb_h,
&cmd_buffer->pool->alloc); &cmd_buffer->pool->alloc);

10
src/amd/vulkan/radv_meta_resolve.c
View File

@@ -609,7 +609,7 @@ void radv_CmdResolveImage(
&cmd_buffer->pool->alloc, &cmd_buffer->pool->alloc,
&fb_h); &fb_h);
radv_CmdBeginRenderPass(cmd_buffer_h, radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.resolve.pass[fs_key], .renderPass = device->meta_state.resolve.pass[fs_key],
@@ -626,8 +626,10 @@ void radv_CmdResolveImage(
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, });
VK_SUBPASS_CONTENTS_INLINE);
radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]);
emit_resolve(cmd_buffer, emit_resolve(cmd_buffer,
dest_iview.vk_format, dest_iview.vk_format,
@@ -640,7 +642,7 @@ void radv_CmdResolveImage(
.height = extent.height, .height = extent.height,
}); });
radv_CmdEndRenderPass(cmd_buffer_h); radv_cmd_buffer_end_render_pass(cmd_buffer);
radv_DestroyFramebuffer(device_h, fb_h, radv_DestroyFramebuffer(device_h, fb_h,
&cmd_buffer->pool->alloc); &cmd_buffer->pool->alloc);

9
src/amd/vulkan/radv_meta_resolve_fs.c
View File

@@ -1127,7 +1127,7 @@ void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
.layers = 1 .layers = 1
}, &cmd_buffer->pool->alloc, &fb); }, &cmd_buffer->pool->alloc, &fb);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), radv_cmd_buffer_begin_render_pass(cmd_buffer,
&(VkRenderPassBeginInfo) { &(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = rp, .renderPass = rp,
@@ -1138,9 +1138,10 @@ void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
}, },
.clearValueCount = 0, .clearValueCount = 0,
.pClearValues = NULL, .pClearValues = NULL,
}, VK_SUBPASS_CONTENTS_INLINE); });
radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]);
emit_resolve(cmd_buffer, emit_resolve(cmd_buffer,
&src_iview, &src_iview,
@@ -1149,7 +1150,7 @@ void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
&(VkOffset2D) { dstOffset.x, dstOffset.y }, &(VkOffset2D) { dstOffset.x, dstOffset.y },
&(VkExtent2D) { extent.width, extent.height }); &(VkExtent2D) { extent.width, extent.height });
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer)); radv_cmd_buffer_end_render_pass(cmd_buffer);
radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc); radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc);
} }

4
src/amd/vulkan/radv_private.h
View File

@@ -2487,6 +2487,10 @@ si_conv_gl_prim_to_vertices(unsigned gl_prim)
} }
} }
void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
const VkRenderPassBeginInfo *pRenderPassBegin);
void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
#define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \ #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
\ \
static inline struct __radv_type * \ static inline struct __radv_type * \