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anv: Drop has_slm in emit_l3_config for gen11+

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For some gen12+ platforms, L3 config (cfg) can be NULL leading to a
seg-fault in emit_l3_config. But, we don't use has_slm for gen11+, so
we can just avoid declaring the variable.

Reworks:
 * Drop has_slm variable for all gens (suggested-by Jason)

Ref: 633dec7163 ("anv: Set L3 full way allocation at context init if L3 cfg is NULL")
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9534
Fixes: 581e68bc99 ("anv: move L3 config emission to genX_state.c")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9589>
This commit is contained in:
Jordan Justen
2021-03-14 12:54:26 -07:00
parent b1ab69f467
commit b6875b0094
1 changed files with 3 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/intel/vulkan/genX_state.c
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@@ -341,7 +341,6 @@ genX(emit_l3_config)(struct anv_batch *batch,
const struct intel_l3_config *cfg)
{
UNUSED const struct gen_device_info *devinfo = &device->info;
UNUSED const bool has_slm = cfg->n[INTEL_L3P_SLM];
#if GEN_GEN >= 8
@@ -362,7 +361,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
#endif
} else {
#if GEN_GEN < 11
l3cr.SLMEnable = has_slm;
l3cr.SLMEnable = cfg->n[INTEL_L3P_SLM];
#endif
#if GEN_GEN == 11
/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be
@@ -399,7 +398,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
* client (URB for all validated configurations) set to the
* lower-bandwidth 2-bank address hashing mode.
*/
const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
const bool urb_low_bw = cfg->n[INTEL_L3P_SLM] && !devinfo->is_baytrail;
assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]);
/* Minimum number of ways that can be allocated to the URB. */
@@ -421,7 +420,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
}
anv_batch_write_reg(batch, GENX(L3CNTLREG2), l3cr2) {
l3cr2.SLMEnable = has_slm;
l3cr2.SLMEnable = cfg->n[INTEL_L3P_SLM];
l3cr2.URBLowBandwidth = urb_low_bw;
l3cr2.URBAllocation = cfg->n[INTEL_L3P_URB] - n0_urb;
#if !GEN_IS_HASWELL