From b4ab54976b7da331175124df0efbf9f1ae69c463 Mon Sep 17 00:00:00 2001
From: Simon Perretta <simon.perretta@imgtec.com>
Date: Wed, 22 Feb 2023 14:00:51 +0000
Subject: [PATCH] pvr: Add encodings for index registers

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>
---
 src/imagination/rogue/rogue_isa.h | 38 +++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/src/imagination/rogue/rogue_isa.h b/src/imagination/rogue/rogue_isa.h
index 3315fbfba4f..a401291a3ab 100644
--- a/src/imagination/rogue/rogue_isa.h
+++ b/src/imagination/rogue/rogue_isa.h
@@ -372,6 +372,33 @@ typedef struct rogue_mux {
 } PACKED rogue_mux;
 static_assert(sizeof(rogue_mux) == 1, "sizeof(rogue_mux) != 1");
 
+typedef struct rogue_idx_offset {
+   union {
+      struct {
+         unsigned bank : 3;
+         unsigned offset : 8;
+         unsigned : 5;
+      } PACKED;
+
+      uint16_t _;
+   } PACKED;
+} PACKED rogue_idx_offset;
+static_assert(sizeof(rogue_idx_offset) == 2, "sizeof(rogue_idx_offset) != 2");
+
+typedef struct rogue_idx_dim_offset {
+   union {
+      struct {
+         unsigned bank : 3;
+         unsigned dim_offset : 5;
+         unsigned : 8;
+      } PACKED;
+
+      uint16_t _;
+   } PACKED;
+} PACKED rogue_idx_dim_offset;
+static_assert(sizeof(rogue_idx_dim_offset) == 2,
+              "sizeof(rogue_idx_dim_offset) != 2");
+
 enum reg_bank {
    BANK_SPECIAL = 0b000,
    BANK_TEMP = 0b001,
@@ -383,6 +410,17 @@ enum reg_bank {
    BANK_IDX1 = 0b111,
 };
 
+enum idx_bank {
+   IDX_BANK_TEMP = 0b000,
+   IDX_BANK_VTXIN = 0b001,
+   IDX_BANK_COEFF = 0b010,
+   IDX_BANK_SHARED = 0b011,
+   IDX_BANK_DC = 0b100,
+   IDX_BANK_IDX = 0b101,
+   IDX_BANK_COEFF_ALT = 0b110,
+   IDX_BANK_PIXOUT = 0b111,
+};
+
 enum is0 {
    IS0_S0 = 0b000,
    IS0_S3 = 0b001,