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pvr: Add encodings for index registers

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Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>
This commit is contained in:
Simon Perretta
2023-02-22 14:00:51 +00:00
committed by Marge Bot
parent 6122dd5488
commit b4ab54976b
1 changed files with 38 additions and 0 deletions
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38
src/imagination/rogue/rogue_isa.h
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@@ -372,6 +372,33 @@ typedef struct rogue_mux {
} PACKED rogue_mux;
static_assert(sizeof(rogue_mux) == 1, "sizeof(rogue_mux) != 1");
typedef struct rogue_idx_offset {
union {
struct {
unsigned bank : 3;
unsigned offset : 8;
unsigned : 5;
} PACKED;
uint16_t _;
} PACKED;
} PACKED rogue_idx_offset;
static_assert(sizeof(rogue_idx_offset) == 2, "sizeof(rogue_idx_offset) != 2");
typedef struct rogue_idx_dim_offset {
union {
struct {
unsigned bank : 3;
unsigned dim_offset : 5;
unsigned : 8;
} PACKED;
uint16_t _;
} PACKED;
} PACKED rogue_idx_dim_offset;
static_assert(sizeof(rogue_idx_dim_offset) == 2,
"sizeof(rogue_idx_dim_offset) != 2");
enum reg_bank {
BANK_SPECIAL = 0b000,
BANK_TEMP = 0b001,
@@ -383,6 +410,17 @@ enum reg_bank {
BANK_IDX1 = 0b111,
};
enum idx_bank {
IDX_BANK_TEMP = 0b000,
IDX_BANK_VTXIN = 0b001,
IDX_BANK_COEFF = 0b010,
IDX_BANK_SHARED = 0b011,
IDX_BANK_DC = 0b100,
IDX_BANK_IDX = 0b101,
IDX_BANK_COEFF_ALT = 0b110,
IDX_BANK_PIXOUT = 0b111,
};
enum is0 {
IS0_S0 = 0b000,
IS0_S3 = 0b001,