mesa: expose AMD_gpu_shader_int64

because the closed driver exposes it.

It's equivalent to ARB_gpu_shader_int64.
In this patch, I did everything the same as we do for ARB_gpu_shader_int64.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Marek Olšák
2018-08-06 00:56:35 -04:00
parent 1cf3631b9c
commit b3c17330e6
9 changed files with 260 additions and 11 deletions

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@@ -535,7 +535,8 @@ static bool
shader_clock_int64(const _mesa_glsl_parse_state *state)
{
return state->ARB_shader_clock_enable &&
state->ARB_gpu_shader_int64_enable;
(state->ARB_gpu_shader_int64_enable ||
state->AMD_gpu_shader_int64_enable);
}
static bool

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@@ -411,7 +411,8 @@ _mesa_glsl_initialize_types(struct _mesa_glsl_parse_state *state)
add_type(symbols, glsl_type::dmat4x3_type);
}
if (state->ARB_gpu_shader_int64_enable) {
if (state->ARB_gpu_shader_int64_enable ||
state->AMD_gpu_shader_int64_enable) {
add_type(symbols, glsl_type::int64_t_type);
add_type(symbols, glsl_type::i64vec2_type);
add_type(symbols, glsl_type::i64vec3_type);

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@@ -664,15 +664,15 @@ sample KEYWORD_WITH_ALT(400, 300, 400, 320, yyextra->ARB_gpu_shader5_enable ||
subroutine KEYWORD_WITH_ALT(400, 300, 400, 0, yyextra->ARB_shader_subroutine_enable, SUBROUTINE);
/* Additional words for ARB_gpu_shader_int64 */
int64_t TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable, glsl_type::int64_t_type);
i64vec2 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable, glsl_type::i64vec2_type);
i64vec3 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable, glsl_type::i64vec3_type);
i64vec4 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable, glsl_type::i64vec4_type);
int64_t TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable || yyextra->AMD_gpu_shader_int64_enable, glsl_type::int64_t_type);
i64vec2 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable || yyextra->AMD_gpu_shader_int64_enable, glsl_type::i64vec2_type);
i64vec3 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable || yyextra->AMD_gpu_shader_int64_enable, glsl_type::i64vec3_type);
i64vec4 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable || yyextra->AMD_gpu_shader_int64_enable, glsl_type::i64vec4_type);
uint64_t TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable, glsl_type::uint64_t_type);
u64vec2 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable, glsl_type::u64vec2_type);
u64vec3 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable, glsl_type::u64vec3_type);
u64vec4 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable, glsl_type::u64vec4_type);
uint64_t TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable || yyextra->AMD_gpu_shader_int64_enable, glsl_type::uint64_t_type);
u64vec2 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable || yyextra->AMD_gpu_shader_int64_enable, glsl_type::u64vec2_type);
u64vec3 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable || yyextra->AMD_gpu_shader_int64_enable, glsl_type::u64vec3_type);
u64vec4 TYPE_WITH_ALT(0, 0, 0, 0, yyextra->ARB_gpu_shader_int64_enable || yyextra->AMD_gpu_shader_int64_enable, glsl_type::u64vec4_type);
[_a-zA-Z][_a-zA-Z0-9]* {
struct _mesa_glsl_parse_state *state = yyextra;

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@@ -699,6 +699,7 @@ static const _mesa_glsl_extension _mesa_glsl_supported_extensions[] = {
/* All other extensions go here, sorted alphabetically.
*/
EXT(AMD_conservative_depth),
EXT(AMD_gpu_shader_int64),
EXT(AMD_shader_stencil_export),
EXT(AMD_shader_trinary_minmax),
EXT(AMD_vertex_shader_layer),

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@@ -256,7 +256,8 @@ struct _mesa_glsl_parse_state {
bool has_int64() const
{
return ARB_gpu_shader_int64_enable;
return ARB_gpu_shader_int64_enable ||
AMD_gpu_shader_int64_enable;
}
bool has_420pack() const
@@ -759,6 +760,8 @@ struct _mesa_glsl_parse_state {
*/
bool AMD_conservative_depth_enable;
bool AMD_conservative_depth_warn;
bool AMD_gpu_shader_int64_enable;
bool AMD_gpu_shader_int64_warn;
bool AMD_shader_stencil_export_enable;
bool AMD_shader_stencil_export_warn;
bool AMD_shader_trinary_minmax_enable;