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intel/isl: Add some basic info about RENDER_SURFACE_STATE to isl_device

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Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Jason Ekstrand
2016-09-19 22:04:40 -07:00
parent ba349e106e
commit b3bc806855
6 changed files with 69 additions and 62 deletions
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33
src/intel/blorp/blorp_genX_exec.h
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@@ -996,28 +996,13 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
return offset; return offset;
} }
struct surface_state_info {
unsigned num_dwords;
unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes */
unsigned reloc_dw;
unsigned aux_reloc_dw;
};
static const struct surface_state_info surface_state_infos[] = {
[6] = {6, 32, 1, 0},
[7] = {8, 32, 1, 6},
[8] = {13, 64, 8, 10},
[9] = {16, 64, 8, 10},
};
static void static void
blorp_emit_surface_state(struct blorp_batch *batch, blorp_emit_surface_state(struct blorp_batch *batch,
const struct brw_blorp_surface_info *surface, const struct brw_blorp_surface_info *surface,
uint32_t *state, uint32_t state_offset, void *state, uint32_t state_offset,
bool is_render_target) bool is_render_target)
{ {
const struct surface_state_info ss_info = surface_state_infos[GEN_GEN]; const struct isl_device *isl_dev = batch->blorp->isl_dev;
struct isl_surf surf = surface->surf; struct isl_surf surf = surface->surf;
if (surf.dim == ISL_SURF_DIM_1D && if (surf.dim == ISL_SURF_DIM_1D &&
@@ -1039,7 +1024,7 @@ blorp_emit_surface_state(struct blorp_batch *batch,
.aux_surf = &surface->aux_surf, .aux_usage = aux_usage, .aux_surf = &surface->aux_surf, .aux_usage = aux_usage,
.mocs = mocs, .clear_color = surface->clear_color); .mocs = mocs, .clear_color = surface->clear_color);
blorp_surface_reloc(batch, state_offset + ss_info.reloc_dw * 4, blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
surface->addr, 0); surface->addr, 0);
if (aux_usage != ISL_AUX_USAGE_NONE) { if (aux_usage != ISL_AUX_USAGE_NONE) {
@@ -1048,8 +1033,9 @@ blorp_emit_surface_state(struct blorp_batch *batch,
* surface buffer addresses are always 4K page alinged. * surface buffer addresses are always 4K page alinged.
*/ */
assert((surface->aux_addr.offset & 0xfff) == 0); assert((surface->aux_addr.offset & 0xfff) == 0);
blorp_surface_reloc(batch, state_offset + ss_info.aux_reloc_dw * 4, uint32_t *aux_addr = state + isl_dev->ss.aux_addr_offset;
surface->aux_addr, state[ss_info.aux_reloc_dw]); blorp_surface_reloc(batch, state_offset + isl_dev->ss.aux_addr_offset,
surface->aux_addr, *aux_addr);
} }
} }
@@ -1087,14 +1073,13 @@ static void
blorp_emit_surface_states(struct blorp_batch *batch, blorp_emit_surface_states(struct blorp_batch *batch,
const struct blorp_params *params) const struct blorp_params *params)
{ {
const struct isl_device *isl_dev = batch->blorp->isl_dev;
uint32_t bind_offset, surface_offsets[2]; uint32_t bind_offset, surface_offsets[2];
void *surface_maps[2]; void *surface_maps[2];
const unsigned ss_size = GENX(RENDER_SURFACE_STATE_length) * 4;
const unsigned ss_align = GENX(RENDER_SURFACE_STATE_length) > 8 ? 64 : 32;
unsigned num_surfaces = 1 + params->src.enabled; unsigned num_surfaces = 1 + params->src.enabled;
blorp_alloc_binding_table(batch, num_surfaces, ss_size, ss_align, blorp_alloc_binding_table(batch, num_surfaces,
isl_dev->ss.size, isl_dev->ss.align,
&bind_offset, surface_offsets, surface_maps); &bind_offset, surface_offsets, surface_maps);
if (params->dst.enabled) { if (params->dst.enabled) {

19
src/intel/isl/isl.c
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@@ -46,6 +46,20 @@ __isl_finishme(const char *file, int line, const char *fmt, ...)
fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf); fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf);
} }
static const struct {
uint8_t size;
uint8_t align;
uint8_t addr_offset;
uint8_t aux_addr_offset;
} ss_infos[] = {
[4] = {24, 32, 4},
[5] = {24, 32, 4},
[6] = {24, 32, 4},
[7] = {32, 32, 4, 24},
[8] = {52, 64, 32, 40},
[9] = {64, 64, 32, 40},
};
void void
isl_device_init(struct isl_device *dev, isl_device_init(struct isl_device *dev,
const struct gen_device_info *info, const struct gen_device_info *info,
@@ -67,6 +81,11 @@ isl_device_init(struct isl_device *dev,
assert(info->has_hiz_and_separate_stencil); assert(info->has_hiz_and_separate_stencil);
if (info->must_use_separate_stencil) if (info->must_use_separate_stencil)
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev)); assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
dev->ss.size = ss_infos[ISL_DEV_GEN(dev)].size;
dev->ss.align = ss_infos[ISL_DEV_GEN(dev)].align;
dev->ss.addr_offset = ss_infos[ISL_DEV_GEN(dev)].addr_offset;
dev->ss.aux_addr_offset = ss_infos[ISL_DEV_GEN(dev)].aux_addr_offset;
} }
/** /**

11
src/intel/isl/isl.h
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@@ -671,6 +671,17 @@ struct isl_device {
const struct gen_device_info *info; const struct gen_device_info *info;
bool use_separate_stencil; bool use_separate_stencil;
bool has_bit6_swizzling; bool has_bit6_swizzling;
/**
* Describes the layout of a RENDER_SURFACE_STATE structure for the
* current gen.
*/
struct {
uint8_t size;
uint8_t align;
uint8_t addr_offset;
uint8_t aux_addr_offset;
} ss;
}; };
struct isl_extent2d { struct isl_extent2d {

4
src/intel/vulkan/anv_batch_chain.c
View File

@@ -620,7 +620,9 @@ anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
struct anv_state struct anv_state
anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer) anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer)
{ {
return anv_state_stream_alloc(&cmd_buffer->surface_state_stream, 64, 64); struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
return anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
isl_dev->ss.size, isl_dev->ss.align);
} }
struct anv_state struct anv_state

8
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -622,14 +622,10 @@ add_surface_state_reloc(struct anv_cmd_buffer *cmd_buffer,
struct anv_state state, struct anv_bo *bo, struct anv_state state, struct anv_bo *bo,
uint32_t offset) uint32_t offset)
{ {
/* The address goes in SURFACE_STATE dword 1 for gens < 8 and dwords 8 and const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
* 9 for gen8+. We only write the first dword for gen8+ here and rely on
* the initial state to set the high bits to 0. */
const uint32_t dword = GEN_GEN < 8 ? 1 : 8;
anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc, anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
state.offset + dword * 4, bo, offset); state.offset + isl_dev->ss.addr_offset, bo, offset);
} }
static struct anv_state static struct anv_state

56
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@@ -60,22 +60,16 @@ enum {
INTEL_AUX_BUFFER_DISABLED = 1 << 1, INTEL_AUX_BUFFER_DISABLED = 1 << 1,
}; };
struct surface_state_info { uint32_t tex_mocs[] = {
unsigned num_dwords; [7] = GEN7_MOCS_L3,
unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes */ [8] = BDW_MOCS_WB,
unsigned reloc_dw; [9] = SKL_MOCS_WB,
unsigned aux_reloc_dw;
unsigned tex_mocs;
unsigned rb_mocs;
}; };
static const struct surface_state_info surface_state_infos[] = { uint32_t rb_mocs[] = {
[4] = {6, 32, 1, 0}, [7] = GEN7_MOCS_L3,
[5] = {6, 32, 1, 0}, [8] = BDW_MOCS_PTE,
[6] = {6, 32, 1, 0}, [9] = SKL_MOCS_PTE,
[7] = {8, 32, 1, 6, GEN7_MOCS_L3, GEN7_MOCS_L3},
[8] = {13, 64, 8, 10, BDW_MOCS_WB, BDW_MOCS_PTE},
[9] = {16, 64, 8, 10, SKL_MOCS_WB, SKL_MOCS_PTE},
}; };
static void static void
@@ -85,7 +79,6 @@ brw_emit_surface_state(struct brw_context *brw,
uint32_t mocs, uint32_t *surf_offset, int surf_index, uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains) unsigned read_domains, unsigned write_domains)
{ {
const struct surface_state_info ss_info = surface_state_infos[brw->gen];
uint32_t tile_x = mt->level[0].slice[0].x_offset; uint32_t tile_x = mt->level[0].slice[0].x_offset;
uint32_t tile_y = mt->level[0].slice[0].y_offset; uint32_t tile_y = mt->level[0].slice[0].y_offset;
uint32_t offset = mt->offset; uint32_t offset = mt->offset;
@@ -164,11 +157,12 @@ brw_emit_surface_state(struct brw_context *brw,
clear_color = intel_miptree_get_isl_clear_color(brw, mt); clear_color = intel_miptree_get_isl_clear_color(brw, mt);
} }
uint32_t *dw = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, void *state = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
ss_info.num_dwords * 4, ss_info.ss_align, brw->isl_dev.ss.size,
surf_index, surf_offset); brw->isl_dev.ss.align,
surf_index, surf_offset);
isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = &view, isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view,
.address = mt->bo->offset64 + offset, .address = mt->bo->offset64 + offset,
.aux_surf = aux_surf, .aux_usage = aux_usage, .aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset, .aux_address = aux_offset,
@@ -176,7 +170,7 @@ brw_emit_surface_state(struct brw_context *brw,
.x_offset_sa = tile_x, .y_offset_sa = tile_y); .x_offset_sa = tile_x, .y_offset_sa = tile_y);
drm_intel_bo_emit_reloc(brw->batch.bo, drm_intel_bo_emit_reloc(brw->batch.bo,
*surf_offset + 4 * ss_info.reloc_dw, *surf_offset + brw->isl_dev.ss.addr_offset,
mt->bo, offset, mt->bo, offset,
read_domains, write_domains); read_domains, write_domains);
@@ -188,9 +182,10 @@ brw_emit_surface_state(struct brw_context *brw,
* an ordinary reloc to do the necessary address translation. * an ordinary reloc to do the necessary address translation.
*/ */
assert((aux_offset & 0xfff) == 0); assert((aux_offset & 0xfff) == 0);
uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset;
drm_intel_bo_emit_reloc(brw->batch.bo, drm_intel_bo_emit_reloc(brw->batch.bo,
*surf_offset + 4 * ss_info.aux_reloc_dw, *surf_offset + brw->isl_dev.ss.aux_addr_offset,
aux_bo, dw[ss_info.aux_reloc_dw] & 0xfff, aux_bo, *aux_addr & 0xfff,
read_domains, write_domains); read_domains, write_domains);
} }
} }
@@ -235,7 +230,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
uint32_t offset; uint32_t offset;
brw_emit_surface_state(brw, mt, flags, mt->target, view, brw_emit_surface_state(brw, mt, flags, mt->target, view,
surface_state_infos[brw->gen].rb_mocs, rb_mocs[brw->gen],
&offset, surf_index, &offset, surf_index,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER); I915_GEM_DOMAIN_RENDER);
@@ -636,7 +631,7 @@ brw_update_texture_surface(struct gl_context *ctx,
const int flags = const int flags =
brw_disable_aux_surface(brw, mt) ? INTEL_AUX_BUFFER_DISABLED : 0; brw_disable_aux_surface(brw, mt) ? INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, mt, flags, mt->target, view, brw_emit_surface_state(brw, mt, flags, mt->target, view,
surface_state_infos[brw->gen].tex_mocs, tex_mocs[brw->gen],
surf_offset, surf_index, surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0); I915_GEM_DOMAIN_SAMPLER, 0);
} }
@@ -652,10 +647,9 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
unsigned pitch, unsigned pitch,
bool rw) bool rw)
{ {
const struct surface_state_info ss_info = surface_state_infos[brw->gen];
uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
ss_info.num_dwords * 4, ss_info.ss_align, brw->isl_dev.ss.size,
brw->isl_dev.ss.align,
out_offset); out_offset);
isl_buffer_fill_state(&brw->isl_dev, dw, isl_buffer_fill_state(&brw->isl_dev, dw,
@@ -663,11 +657,11 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
.size = buffer_size, .size = buffer_size,
.format = surface_format, .format = surface_format,
.stride = pitch, .stride = pitch,
.mocs = ss_info.tex_mocs); .mocs = tex_mocs[brw->gen]);
if (bo) { if (bo) {
drm_intel_bo_emit_reloc(brw->batch.bo, drm_intel_bo_emit_reloc(brw->batch.bo,
*out_offset + 4 * ss_info.reloc_dw, *out_offset + brw->isl_dev.ss.addr_offset,
bo, buffer_offset, bo, buffer_offset,
I915_GEM_DOMAIN_SAMPLER, I915_GEM_DOMAIN_SAMPLER,
(rw ? I915_GEM_DOMAIN_SAMPLER : 0)); (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
@@ -1209,7 +1203,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
const int flags = brw->draw_aux_buffer_disabled[i] ? const int flags = brw->draw_aux_buffer_disabled[i] ?
INTEL_AUX_BUFFER_DISABLED : 0; INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, irb->mt, flags, target, view, brw_emit_surface_state(brw, irb->mt, flags, target, view,
surface_state_infos[brw->gen].tex_mocs, tex_mocs[brw->gen],
surf_offset, surf_index, surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0); I915_GEM_DOMAIN_SAMPLER, 0);
@@ -1766,7 +1760,7 @@ update_image_surface(struct brw_context *brw,
mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED ? mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED ?
INTEL_AUX_BUFFER_DISABLED : 0; INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, mt, flags, mt->target, view, brw_emit_surface_state(brw, mt, flags, mt->target, view,
surface_state_infos[brw->gen].tex_mocs, tex_mocs[brw->gen],
surf_offset, surf_index, surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, I915_GEM_DOMAIN_SAMPLER,
access == GL_READ_ONLY ? 0 : access == GL_READ_ONLY ? 0 :