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radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK

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It has probably no effect without out of order rasterization
anyway.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2018-10-03 16:09:24 +02:00
parent 937986ca1d
commit b38228ccb0
1 changed files with 2 additions and 2 deletions
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4
src/amd/vulkan/radv_pipeline.c
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@@ -1081,6 +1081,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
ms->pa_sc_mode_cntl_1 =
S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
/* always 1: */
S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
@@ -1124,8 +1125,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
}
if (out_of_order_rast) {
ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1);
}
if (vkms && vkms->pSampleMask) {