radv: remove radv_graphics_pipeline::vb_desc_usage_mask

Use the VS shader info instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22192>

src/amd/vulkan/radv_cmd_buffer.c

@@ -4716,7 +4716,7 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer,
    enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level;
    enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
    unsigned desc_index = 0;
-   uint32_t mask = pipeline->vb_desc_usage_mask;
+   uint32_t mask = vs_shader->info.vs.vb_desc_usage_mask;
    uint64_t va;
    const struct radv_vs_input_state *vs_state =
       vs_shader->info.vs.dynamic_inputs ? &cmd_buffer->state.dynamic_vs_input : NULL;
@@ -4879,14 +4879,15 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer,
 static void
 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
 {
-   if (!cmd_buffer->state.graphics_pipeline->vb_desc_usage_mask)
+   struct radv_shader *vs = radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_VERTEX);
+
+   if (!vs->info.vs.vb_desc_usage_mask)
       return;
 
    /* Mesh shaders don't have vertex descriptors. */
    assert(!cmd_buffer->state.mesh_shading);
 
    struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
-   struct radv_shader *vs = radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_VERTEX);
    unsigned vb_offset;
    void *vb_ptr;
    uint64_t va;
@@ -6538,7 +6539,8 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
       }
 
       /* Re-emit the vertex buffer descriptors because they are really tied to the pipeline. */
-      if (graphics_pipeline->vb_desc_usage_mask) {
+      if (graphics_pipeline->base.shaders[MESA_SHADER_VERTEX] &&
+          graphics_pipeline->base.shaders[MESA_SHADER_VERTEX]->info.vs.vb_desc_usage_mask) {
          cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
       }
 

src/amd/vulkan/radv_debug.c

@@ -422,7 +422,7 @@ radv_dump_vertex_descriptors(const struct radv_device *device,
 {
    struct radv_shader *vs = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX);
    void *ptr = (uint64_t *)device->trace_id_ptr;
-   uint32_t count = util_bitcount(pipeline->vb_desc_usage_mask);
+   uint32_t count = util_bitcount(vs->info.vs.vb_desc_usage_mask);
    uint32_t *vb_ptr = &((uint32_t *)ptr)[3];
 
    if (!count)

src/amd/vulkan/radv_device_generated_commands.c

@@ -34,11 +34,12 @@ radv_get_sequence_size(const struct radv_indirect_command_layout *layout,
                        uint32_t *upload_size)
 {
    const struct radv_device *device = container_of(layout->base.device, struct radv_device, vk);
+   const struct radv_shader *vs = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX);
    *cmd_size = 0;
    *upload_size = 0;
 
    if (layout->bind_vbo_mask) {
-      *upload_size += 16 * util_bitcount(pipeline->vb_desc_usage_mask);
+      *upload_size += 16 * util_bitcount(vs->info.vs.vb_desc_usage_mask);
 
      /* One PKT3_SET_SH_REG for emitting VBO pointer (32-bit) */
       *cmd_size += 3 * 4;
@@ -1107,6 +1108,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer,
    VK_FROM_HANDLE(radv_pipeline, pipeline, pGeneratedCommandsInfo->pipeline);
    VK_FROM_HANDLE(radv_buffer, prep_buffer, pGeneratedCommandsInfo->preprocessBuffer);
    struct radv_graphics_pipeline *graphics_pipeline = radv_pipeline_to_graphics(pipeline);
+   struct radv_shader *vs = radv_get_shader(graphics_pipeline->base.shaders, MESA_SHADER_VERTEX);
    struct radv_meta_saved_state saved_state;
    struct radv_buffer token_buffer;
 
@@ -1116,7 +1118,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer,
    unsigned cmd_buf_size =
       radv_align_cmdbuf_size(cmd_stride * pGeneratedCommandsInfo->sequencesCount);
 
-   unsigned vb_size = layout->bind_vbo_mask ? util_bitcount(graphics_pipeline->vb_desc_usage_mask) * 24 : 0;
+   unsigned vb_size = layout->bind_vbo_mask ? util_bitcount(vs->info.vs.vb_desc_usage_mask) * 24 : 0;
    unsigned const_size = graphics_pipeline->base.push_constant_size +
                          16 * graphics_pipeline->base.dynamic_offset_count +
                          sizeof(layout->push_constant_offsets) + ARRAY_SIZE(graphics_pipeline->base.shaders) * 12;
@@ -1185,7 +1187,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer,
 
       uint32_t *vbo_info = (uint32_t *)((char *)upload_data + graphics_pipeline->vb_desc_alloc_size);
 
-      uint32_t mask = graphics_pipeline->vb_desc_usage_mask;
+      uint32_t mask = vertex_shader->info.vs.vb_desc_usage_mask;
       unsigned idx = 0;
       while (mask) {
          unsigned i = u_bit_scan(&mask);

src/amd/vulkan/radv_pipeline.c

@@ -4409,11 +4409,7 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device,
       }
    }
 
-   if (vs_info->vs.dynamic_inputs)
-      pipeline->vb_desc_usage_mask = BITFIELD_MASK(util_last_bit(vs_info->vs.vb_desc_usage_mask));
-   else
-      pipeline->vb_desc_usage_mask = vs_info->vs.vb_desc_usage_mask;
-   pipeline->vb_desc_alloc_size = util_bitcount(pipeline->vb_desc_usage_mask) * 16;
+   pipeline->vb_desc_alloc_size = util_bitcount(vs_info->vs.vb_desc_usage_mask) * 16;
 
    /* Prepare the VS input state for prologs created inside a library. */
    if (vs_info->vs.has_prolog && !(pipeline->dynamic_states & RADV_DYNAMIC_VERTEX_INPUT)) {

src/amd/vulkan/radv_private.h

@@ -2239,7 +2239,6 @@ struct radv_graphics_pipeline {
    uint8_t attrib_bindings[MAX_VERTEX_ATTRIBS];
    uint32_t attrib_ends[MAX_VERTEX_ATTRIBS];
    uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS];
-   uint32_t vb_desc_usage_mask;
    uint32_t vb_desc_alloc_size;
    uint32_t pa_sc_mode_cntl_1;
    uint32_t db_render_control;