OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Revert "radeonsi: set BIG_PAGE fields on gfx10.3"

Browse Source 
This reverts commit 430d384c31.

BIT_PAGE can't be set for GTT and we don't know if a buffer has been
evicted to GTT.

Fixes: 430d384c31

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6722>
This commit is contained in:
Marek Olšák
2020-09-14 20:59:36 -04:00
committed by Marge Bot
parent 758ab39d25
commit b23013db0a
2 changed files with 3 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/radeonsi/si_pipe.h
View File

@@ -715,8 +715,6 @@ struct si_framebuffer {
bool CB_has_shader_readable_metadata;
bool DB_has_shader_readable_metadata;
bool all_DCC_pipe_aligned;
bool color_big_page;
bool zs_big_page;
};
enum si_quant_mode

24
src/gallium/drivers/radeonsi/si_state.c
View File

@@ -2703,8 +2703,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
sctx->framebuffer.DB_has_shader_readable_metadata = false;
sctx->framebuffer.all_DCC_pipe_aligned = true;
sctx->framebuffer.min_bytes_per_pixel = 0;
sctx->framebuffer.color_big_page = true;
sctx->framebuffer.zs_big_page = true;
for (i = 0; i < state->nr_cbufs; i++) {
if (!state->cbufs[i])
@@ -2724,9 +2722,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
sctx->framebuffer.spi_shader_col_format_blend_alpha |= surf->spi_shader_col_format_blend_alpha
<< (i * 4);
sctx->framebuffer.color_big_page &=
tex->buffer.bo_alignment % (64 * 1024) == 0;
if (surf->color_is_int8)
sctx->framebuffer.color_is_int8 |= 1 << i;
if (surf->color_is_int10)
@@ -2792,8 +2787,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
si_init_depth_surface(sctx, surf);
}
sctx->framebuffer.zs_big_page = zstex->buffer.bo_alignment % (64 * 1024) == 0;
if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
sctx->framebuffer.DB_has_shader_readable_metadata = true;
@@ -3134,9 +3127,6 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
}
if (sctx->chip_class >= GFX10) {
bool zs_big_page = sctx->chip_class >= GFX10_3 &&
sctx->framebuffer.zs_big_page;
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
@@ -3163,9 +3153,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) |
S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) |
S_02807C_HTILE_RD_POLICY(meta_read_policy) |
S_02807C_Z_BIG_PAGE(zs_big_page) |
S_02807C_S_BIG_PAGE(zs_big_page));
S_02807C_HTILE_RD_POLICY(meta_read_policy));
} else if (sctx->chip_class == GFX9) {
radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
@@ -3253,8 +3241,6 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
if (nr_cbufs) {
bool color_big_page = sctx->chip_class >= GFX10_3 &&
sctx->framebuffer.color_big_page;
radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
S_028410_CMASK_WR_POLICY(meta_write_policy) |
S_028410_FMASK_WR_POLICY(meta_write_policy) |
@@ -3263,9 +3249,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
S_028410_CMASK_RD_POLICY(meta_read_policy) |
S_028410_FMASK_RD_POLICY(meta_read_policy) |
S_028410_DCC_RD_POLICY(meta_read_policy) |
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA) |
S_028410_FMASK_BIG_PAGE(color_big_page) |
S_028410_COLOR_BIG_PAGE(color_big_page));
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA));
}
if (sctx->screen->dfsm_allowed) {
@@ -3756,9 +3740,7 @@ static void gfx10_make_texture_descriptor(
state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
S_00A014_MAX_MIP(res->nr_samples > 1 ? util_logbase2(res->nr_samples)
: tex->buffer.b.b.last_level) |
S_00A014_PERF_MOD(4) |
S_00A014_BIG_PAGE(screen->info.chip_class >= GFX10_3 &&
tex->buffer.bo_alignment % (64 * 1024) == 0);
S_00A014_PERF_MOD(4);
state[6] = 0;
state[7] = 0;