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radv: force using indirect descriptor sets for indirect compute pipelines

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Emitting descriptors in DGC is a huge pain but using indirect descriptor
sets is much easier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29700>
This commit is contained in:
Samuel Pitoiset
2024-06-12 18:00:02 +02:00
committed by Marge Bot
parent ef21df917f
commit b1ba02e707
8 changed files with 17 additions and 12 deletions
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3
src/amd/vulkan/radv_shader_info.c
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@@ -1121,7 +1121,7 @@ void
radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir,
const struct radv_shader_layout *layout, const struct radv_shader_stage_key *stage_key,
const struct radv_graphics_state_key *gfx_state, const enum radv_pipeline_type pipeline_type,
bool consider_force_vrs, struct radv_shader_info *info)
bool consider_force_vrs, bool is_indirect_bindable, struct radv_shader_info *info)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
@@ -1232,6 +1232,7 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
info->user_data_0 = radv_get_user_data_0(device, info);
info->merged_shader_compiled_separately = radv_is_merged_shader_compiled_separately(device, info);
info->force_indirect_desc_sets = info->merged_shader_compiled_separately || is_indirect_bindable;
switch (nir->info.stage) {
case MESA_SHADER_COMPUTE: