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radv: configure DB_Z_INFO.NUM_SAMPLES on GFX12

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Similar to GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29482>
This commit is contained in:
Samuel Pitoiset
2024-05-28 11:52:00 +02:00
committed by Marge Bot
parent 1e0b838c7b
commit b1abbfb893
1 changed files with 7 additions and 8 deletions
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15
src/amd/vulkan/radv_cmd_buffer.c
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@@ -4124,15 +4124,8 @@ radv_emit_null_ds_state(struct radv_cmd_buffer *cmd_buffer)
const struct radv_physical_device *pdev = radv_device_physical(device); const struct radv_physical_device *pdev = radv_device_physical(device);
const enum amd_gfx_level gfx_level = pdev->info.gfx_level; const enum amd_gfx_level gfx_level = pdev->info.gfx_level;
unsigned db_render_control = 0; unsigned db_render_control = 0;
unsigned num_samples = 0;
/* On GFX11, the hw intentionally looks at DB_Z_INFO.NUM_SAMPLES when there is no bound
* depth/stencil buffer and it clamps the number of samples like MIN2(DB_Z_INFO.NUM_SAMPLES,
* PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES). Use 8x for DB_Z_INFO.NUM_SAMPLES to make sure it's not
* the constraining factor. This affects VRS, occlusion queries and POPS.
*/
if (gfx_level == GFX11) { if (gfx_level == GFX11) {
num_samples = 3;
radv_gfx11_set_db_render_control(device, 1, &db_render_control); radv_gfx11_set_db_render_control(device, 1, &db_render_control);
} }
@@ -4142,7 +4135,13 @@ radv_emit_null_ds_state(struct radv_cmd_buffer *cmd_buffer)
radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2); radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
} }
radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID) | S_028040_NUM_SAMPLES(num_samples)); /* On GFX11+, the hw intentionally looks at DB_Z_INFO.NUM_SAMPLES when there is no bound
* depth/stencil buffer and it clamps the number of samples like MIN2(DB_Z_INFO.NUM_SAMPLES,
* PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES). Use 8x for DB_Z_INFO.NUM_SAMPLES to make sure it's not
* the constraining factor. This affects VRS, occlusion queries and POPS.
*/
radeon_emit(cmd_buffer->cs,
S_028040_FORMAT(V_028040_Z_INVALID) | S_028040_NUM_SAMPLES(pdev->info.gfx_level >= GFX11 ? 3 : 0));
radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID));
radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, db_render_control); radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, db_render_control);