radv: add radv_shader_info.h
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28551>
This commit is contained in:
Samuel Pitoiset
committed by
Marge Bot
Marge Bot
parent
fb73ccea56
commit
b171bc2809
@@ -165,6 +165,7 @@ libradv_files = files(
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'radv_shader_args.c',
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'radv_shader_args.h',
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'radv_shader_info.c',
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'radv_shader_info.h',
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'radv_shader_object.c',
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'radv_shader_object.h',
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'radv_spm.c',
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@@ -174,4 +174,6 @@
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*/
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#define RADV_SDMA_TRANSFER_TEMP_BYTES (2 * (1 << 14) * 16)
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#define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
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#endif /* RADV_CONSTANTS_H */
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@@ -36,12 +36,11 @@
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#include "amd_family.h"
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#include "radv_constants.h"
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#include "radv_shader_args.h"
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#include "radv_shader_info.h"
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#include "vk_pipeline_cache.h"
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#include "aco_shader_info.h"
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#define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
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struct radv_physical_device;
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struct radv_device;
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struct radv_pipeline;
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@@ -240,229 +239,6 @@ struct radv_nir_compiler_options {
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#define PS_STATE_RAST_PRIM__SHIFT 22
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#define PS_STATE_RAST_PRIM__MASK 0x3
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struct radv_streamout_info {
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uint16_t num_outputs;
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uint16_t strides[MAX_SO_BUFFERS];
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uint32_t enabled_stream_buffers_mask;
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};
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struct radv_vs_output_info {
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uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
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uint8_t clip_dist_mask;
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uint8_t cull_dist_mask;
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uint8_t param_exports;
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uint8_t prim_param_exports;
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bool writes_pointsize;
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bool writes_layer;
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bool writes_layer_per_primitive;
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bool writes_viewport_index;
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bool writes_viewport_index_per_primitive;
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bool writes_primitive_shading_rate;
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bool writes_primitive_shading_rate_per_primitive;
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bool export_prim_id;
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unsigned pos_exports;
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};
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struct radv_legacy_gs_info {
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uint32_t vgt_gs_onchip_cntl;
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uint32_t vgt_gs_max_prims_per_subgroup;
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uint32_t vgt_esgs_ring_itemsize;
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uint32_t lds_size;
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uint32_t esgs_ring_size;
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uint32_t gsvs_ring_size;
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};
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struct gfx10_ngg_info {
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uint16_t ngg_emit_size; /* in dwords */
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uint32_t hw_max_esverts;
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uint32_t max_gsprims;
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uint32_t max_out_verts;
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uint32_t prim_amp_factor;
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uint32_t vgt_esgs_ring_itemsize;
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uint32_t esgs_ring_size;
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uint32_t scratch_lds_base;
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uint32_t lds_size;
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bool max_vert_out_per_gs_instance;
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};
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enum radv_shader_type {
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RADV_SHADER_TYPE_DEFAULT = 0,
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RADV_SHADER_TYPE_GS_COPY,
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RADV_SHADER_TYPE_TRAP_HANDLER,
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};
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struct radv_shader_info {
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uint64_t inline_push_constant_mask;
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bool can_inline_all_push_constants;
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bool loads_push_constants;
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bool loads_dynamic_offsets;
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uint32_t desc_set_used_mask;
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bool uses_view_index;
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bool uses_invocation_id;
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bool uses_prim_id;
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uint8_t wave_size;
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uint8_t ballot_bit_size;
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struct radv_userdata_locations user_sgprs_locs;
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bool is_ngg;
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bool is_ngg_passthrough;
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bool has_ngg_culling;
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bool has_ngg_early_prim_export;
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bool has_prim_query;
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bool has_xfb_query;
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uint32_t num_tess_patches;
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uint32_t esgs_itemsize; /* Only for VS or TES as ES */
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struct radv_vs_output_info outinfo;
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unsigned workgroup_size;
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bool force_vrs_per_vertex;
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gl_shader_stage stage;
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gl_shader_stage next_stage;
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enum radv_shader_type type;
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uint32_t user_data_0;
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bool inputs_linked;
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bool outputs_linked;
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bool has_epilog; /* Only for TCS or PS */
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bool merged_shader_compiled_separately; /* GFX9+ */
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struct {
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uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
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bool needs_draw_id;
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bool needs_instance_id;
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bool as_es;
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bool as_ls;
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bool tcs_in_out_eq;
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uint64_t tcs_temp_only_input_mask;
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uint8_t num_linked_outputs;
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bool needs_base_instance;
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bool use_per_attribute_vb_descs;
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uint32_t vb_desc_usage_mask;
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uint32_t input_slot_usage_mask;
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bool has_prolog;
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bool dynamic_inputs;
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bool dynamic_num_verts_per_prim;
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uint32_t num_outputs; /* For NGG streamout only */
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} vs;
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struct {
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uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
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uint8_t num_stream_output_components[4];
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uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
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uint8_t max_stream;
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unsigned gsvs_vertex_size;
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unsigned max_gsvs_emit_size;
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unsigned vertices_in;
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unsigned vertices_out;
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unsigned input_prim;
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unsigned output_prim;
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unsigned invocations;
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unsigned es_type; /* GFX9: VS or TES */
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uint8_t num_linked_inputs;
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bool has_pipeline_stat_query;
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} gs;
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struct {
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uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
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bool as_es;
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enum tess_primitive_mode _primitive_mode;
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enum gl_tess_spacing spacing;
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bool ccw;
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bool point_mode;
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bool reads_tess_factors;
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unsigned tcs_vertices_out;
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uint8_t num_linked_inputs;
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uint8_t num_linked_outputs;
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uint32_t num_outputs; /* For NGG streamout only */
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} tes;
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struct {
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bool uses_sample_shading;
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bool needs_sample_positions;
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bool needs_poly_line_smooth;
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bool writes_memory;
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bool writes_z;
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bool writes_stencil;
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bool writes_sample_mask;
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bool writes_mrt0_alpha;
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bool exports_mrtz_via_epilog;
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bool has_pcoord;
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bool prim_id_input;
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bool layer_input;
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bool viewport_index_input;
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uint8_t input_clips_culls_mask;
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uint32_t input_mask;
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uint32_t input_per_primitive_mask;
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uint32_t flat_shaded_mask;
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uint32_t explicit_shaded_mask;
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uint32_t per_vertex_shaded_mask;
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uint32_t float16_shaded_mask;
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uint32_t num_interp;
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uint32_t num_prim_interp;
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bool can_discard;
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bool early_fragment_test;
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bool post_depth_coverage;
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bool reads_sample_mask_in;
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bool reads_front_face;
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bool reads_sample_id;
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bool reads_frag_shading_rate;
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bool reads_barycentric_model;
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bool reads_persp_sample;
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bool reads_persp_center;
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bool reads_persp_centroid;
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bool reads_linear_sample;
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bool reads_linear_center;
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bool reads_linear_centroid;
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bool reads_fully_covered;
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uint8_t reads_frag_coord_mask;
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uint8_t reads_sample_pos_mask;
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uint8_t depth_layout;
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bool allow_flat_shading;
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bool pops; /* Uses Primitive Ordered Pixel Shading (fragment shader interlock) */
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bool pops_is_per_sample;
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bool mrt0_is_dual_src;
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unsigned spi_ps_input;
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unsigned colors_written;
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unsigned spi_shader_col_format;
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uint8_t color0_written;
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bool load_provoking_vtx;
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bool load_rasterization_prim;
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bool force_sample_iter_shading_rate;
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uint32_t db_shader_control; /* DB_SHADER_CONTROL without intrinsic rate overrides */
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} ps;
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struct {
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bool uses_grid_size;
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bool uses_block_id[3];
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bool uses_thread_id[3];
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bool uses_local_invocation_idx;
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unsigned block_size[3];
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bool is_rt_shader;
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bool uses_dynamic_rt_callable_stack;
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bool uses_rt;
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bool uses_full_subgroups;
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bool linear_taskmesh_dispatch;
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bool has_query; /* Task shader only */
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bool regalloc_hang_bug;
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} cs;
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struct {
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uint64_t tes_inputs_read;
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uint64_t tes_patch_inputs_read;
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unsigned tcs_vertices_out;
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uint32_t num_lds_blocks;
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uint8_t num_linked_inputs;
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uint8_t num_linked_outputs;
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uint8_t num_linked_patch_outputs;
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bool tes_reads_tess_factors : 1;
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} tcs;
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struct {
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enum mesa_prim output_prim;
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bool needs_ms_scratch_ring;
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bool has_task; /* If mesh shader is used together with a task shader. */
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bool has_query;
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} ms;
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struct radv_streamout_info so;
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struct radv_legacy_gs_info gs_ring_info;
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struct gfx10_ngg_info ngg_info;
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};
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struct radv_shader_layout {
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uint32_t num_sets;
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@@ -834,8 +610,6 @@ VkResult radv_dump_shader_stats(struct radv_device *device, struct radv_pipeline
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/* Returns true on success and false on failure */
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bool radv_shader_reupload(struct radv_device *device, struct radv_shader *shader);
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enum ac_hw_stage radv_select_hw_stage(const struct radv_shader_info *const info, const enum amd_gfx_level gfx_level);
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extern const struct vk_pipeline_cache_object_ops radv_shader_ops;
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static inline struct radv_shader *
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@@ -1004,20 +778,6 @@ radv_get_rt_priority(gl_shader_stage stage)
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struct radv_shader_layout;
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enum radv_pipeline_type;
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void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir,
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const struct radv_shader_layout *layout, const struct radv_shader_stage_key *stage_key,
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const struct radv_graphics_state_key *gfx_state,
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const enum radv_pipeline_type pipeline_type, bool consider_force_vrs,
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struct radv_shader_info *info);
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void radv_nir_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, struct radv_shader_info *info);
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void radv_nir_shader_info_link(struct radv_device *device, const struct radv_graphics_state_key *gfx_state,
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struct radv_shader_stage *stages);
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void gfx10_get_ngg_info(const struct radv_device *device, struct radv_shader_info *es_info,
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struct radv_shader_info *gs_info, struct gfx10_ngg_info *out);
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void radv_shader_combine_cfg_vs_tcs(const struct radv_shader *vs, const struct radv_shader *tcs, uint32_t *rsrc1_out,
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uint32_t *rsrc2_out);
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@@ -20,6 +20,7 @@
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "radv_shader_info.h"
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#include "nir/nir.h"
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#include "nir/nir_xfb_info.h"
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#include "nir/radv_nir.h"
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283
src/amd/vulkan/radv_shader_info.h
Normal file
283
src/amd/vulkan/radv_shader_info.h
Normal file
@@ -0,0 +1,283 @@
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/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef RADV_SHADER_INFO_H
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#define RADV_SHADER_INFO_H
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#include <inttypes.h>
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#include <stdbool.h>
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#include "radv_constants.h"
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#include "radv_shader_args.h"
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struct radv_device;
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struct nir_shader;
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struct radv_shader_layout;
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struct radv_shader_stage_key;
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enum radv_pipeline_type;
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struct radv_shader_stage;
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enum radv_shader_type {
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RADV_SHADER_TYPE_DEFAULT = 0,
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RADV_SHADER_TYPE_GS_COPY,
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RADV_SHADER_TYPE_TRAP_HANDLER,
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};
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struct radv_vs_output_info {
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uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
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uint8_t clip_dist_mask;
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uint8_t cull_dist_mask;
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uint8_t param_exports;
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uint8_t prim_param_exports;
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bool writes_pointsize;
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bool writes_layer;
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bool writes_layer_per_primitive;
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bool writes_viewport_index;
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bool writes_viewport_index_per_primitive;
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bool writes_primitive_shading_rate;
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bool writes_primitive_shading_rate_per_primitive;
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bool export_prim_id;
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unsigned pos_exports;
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};
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struct radv_streamout_info {
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uint16_t num_outputs;
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uint16_t strides[MAX_SO_BUFFERS];
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uint32_t enabled_stream_buffers_mask;
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};
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struct radv_legacy_gs_info {
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uint32_t vgt_gs_onchip_cntl;
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uint32_t vgt_gs_max_prims_per_subgroup;
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uint32_t vgt_esgs_ring_itemsize;
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uint32_t lds_size;
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uint32_t esgs_ring_size;
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uint32_t gsvs_ring_size;
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};
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struct gfx10_ngg_info {
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uint16_t ngg_emit_size; /* in dwords */
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uint32_t hw_max_esverts;
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uint32_t max_gsprims;
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uint32_t max_out_verts;
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uint32_t prim_amp_factor;
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uint32_t vgt_esgs_ring_itemsize;
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uint32_t esgs_ring_size;
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uint32_t scratch_lds_base;
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uint32_t lds_size;
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bool max_vert_out_per_gs_instance;
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};
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struct radv_shader_info {
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uint64_t inline_push_constant_mask;
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bool can_inline_all_push_constants;
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bool loads_push_constants;
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bool loads_dynamic_offsets;
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uint32_t desc_set_used_mask;
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bool uses_view_index;
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bool uses_invocation_id;
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bool uses_prim_id;
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uint8_t wave_size;
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uint8_t ballot_bit_size;
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struct radv_userdata_locations user_sgprs_locs;
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bool is_ngg;
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bool is_ngg_passthrough;
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bool has_ngg_culling;
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bool has_ngg_early_prim_export;
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bool has_prim_query;
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bool has_xfb_query;
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uint32_t num_tess_patches;
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uint32_t esgs_itemsize; /* Only for VS or TES as ES */
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struct radv_vs_output_info outinfo;
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unsigned workgroup_size;
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bool force_vrs_per_vertex;
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gl_shader_stage stage;
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gl_shader_stage next_stage;
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enum radv_shader_type type;
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uint32_t user_data_0;
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bool inputs_linked;
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bool outputs_linked;
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bool has_epilog; /* Only for TCS or PS */
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bool merged_shader_compiled_separately; /* GFX9+ */
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struct {
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uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
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bool needs_draw_id;
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bool needs_instance_id;
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bool as_es;
|
||||
bool as_ls;
|
||||
bool tcs_in_out_eq;
|
||||
uint64_t tcs_temp_only_input_mask;
|
||||
uint8_t num_linked_outputs;
|
||||
bool needs_base_instance;
|
||||
bool use_per_attribute_vb_descs;
|
||||
uint32_t vb_desc_usage_mask;
|
||||
uint32_t input_slot_usage_mask;
|
||||
bool has_prolog;
|
||||
bool dynamic_inputs;
|
||||
bool dynamic_num_verts_per_prim;
|
||||
uint32_t num_outputs; /* For NGG streamout only */
|
||||
} vs;
|
||||
struct {
|
||||
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
|
||||
uint8_t num_stream_output_components[4];
|
||||
uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
|
||||
uint8_t max_stream;
|
||||
unsigned gsvs_vertex_size;
|
||||
unsigned max_gsvs_emit_size;
|
||||
unsigned vertices_in;
|
||||
unsigned vertices_out;
|
||||
unsigned input_prim;
|
||||
unsigned output_prim;
|
||||
unsigned invocations;
|
||||
unsigned es_type; /* GFX9: VS or TES */
|
||||
uint8_t num_linked_inputs;
|
||||
bool has_pipeline_stat_query;
|
||||
} gs;
|
||||
struct {
|
||||
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
|
||||
bool as_es;
|
||||
enum tess_primitive_mode _primitive_mode;
|
||||
enum gl_tess_spacing spacing;
|
||||
bool ccw;
|
||||
bool point_mode;
|
||||
bool reads_tess_factors;
|
||||
unsigned tcs_vertices_out;
|
||||
uint8_t num_linked_inputs;
|
||||
uint8_t num_linked_outputs;
|
||||
uint32_t num_outputs; /* For NGG streamout only */
|
||||
} tes;
|
||||
struct {
|
||||
bool uses_sample_shading;
|
||||
bool needs_sample_positions;
|
||||
bool needs_poly_line_smooth;
|
||||
bool writes_memory;
|
||||
bool writes_z;
|
||||
bool writes_stencil;
|
||||
bool writes_sample_mask;
|
||||
bool writes_mrt0_alpha;
|
||||
bool exports_mrtz_via_epilog;
|
||||
bool has_pcoord;
|
||||
bool prim_id_input;
|
||||
bool layer_input;
|
||||
bool viewport_index_input;
|
||||
uint8_t input_clips_culls_mask;
|
||||
uint32_t input_mask;
|
||||
uint32_t input_per_primitive_mask;
|
||||
uint32_t flat_shaded_mask;
|
||||
uint32_t explicit_shaded_mask;
|
||||
uint32_t per_vertex_shaded_mask;
|
||||
uint32_t float16_shaded_mask;
|
||||
uint32_t num_interp;
|
||||
uint32_t num_prim_interp;
|
||||
bool can_discard;
|
||||
bool early_fragment_test;
|
||||
bool post_depth_coverage;
|
||||
bool reads_sample_mask_in;
|
||||
bool reads_front_face;
|
||||
bool reads_sample_id;
|
||||
bool reads_frag_shading_rate;
|
||||
bool reads_barycentric_model;
|
||||
bool reads_persp_sample;
|
||||
bool reads_persp_center;
|
||||
bool reads_persp_centroid;
|
||||
bool reads_linear_sample;
|
||||
bool reads_linear_center;
|
||||
bool reads_linear_centroid;
|
||||
bool reads_fully_covered;
|
||||
uint8_t reads_frag_coord_mask;
|
||||
uint8_t reads_sample_pos_mask;
|
||||
uint8_t depth_layout;
|
||||
bool allow_flat_shading;
|
||||
bool pops; /* Uses Primitive Ordered Pixel Shading (fragment shader interlock) */
|
||||
bool pops_is_per_sample;
|
||||
bool mrt0_is_dual_src;
|
||||
unsigned spi_ps_input;
|
||||
unsigned colors_written;
|
||||
unsigned spi_shader_col_format;
|
||||
uint8_t color0_written;
|
||||
bool load_provoking_vtx;
|
||||
bool load_rasterization_prim;
|
||||
bool force_sample_iter_shading_rate;
|
||||
uint32_t db_shader_control; /* DB_SHADER_CONTROL without intrinsic rate overrides */
|
||||
} ps;
|
||||
struct {
|
||||
bool uses_grid_size;
|
||||
bool uses_block_id[3];
|
||||
bool uses_thread_id[3];
|
||||
bool uses_local_invocation_idx;
|
||||
unsigned block_size[3];
|
||||
|
||||
bool is_rt_shader;
|
||||
bool uses_dynamic_rt_callable_stack;
|
||||
bool uses_rt;
|
||||
bool uses_full_subgroups;
|
||||
bool linear_taskmesh_dispatch;
|
||||
bool has_query; /* Task shader only */
|
||||
|
||||
bool regalloc_hang_bug;
|
||||
} cs;
|
||||
struct {
|
||||
uint64_t tes_inputs_read;
|
||||
uint64_t tes_patch_inputs_read;
|
||||
unsigned tcs_vertices_out;
|
||||
uint32_t num_lds_blocks;
|
||||
uint8_t num_linked_inputs;
|
||||
uint8_t num_linked_outputs;
|
||||
uint8_t num_linked_patch_outputs;
|
||||
bool tes_reads_tess_factors : 1;
|
||||
} tcs;
|
||||
struct {
|
||||
enum mesa_prim output_prim;
|
||||
bool needs_ms_scratch_ring;
|
||||
bool has_task; /* If mesh shader is used together with a task shader. */
|
||||
bool has_query;
|
||||
} ms;
|
||||
|
||||
struct radv_streamout_info so;
|
||||
|
||||
struct radv_legacy_gs_info gs_ring_info;
|
||||
struct gfx10_ngg_info ngg_info;
|
||||
};
|
||||
|
||||
void radv_nir_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, struct radv_shader_info *info);
|
||||
|
||||
void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir,
|
||||
const struct radv_shader_layout *layout, const struct radv_shader_stage_key *stage_key,
|
||||
const struct radv_graphics_state_key *gfx_state,
|
||||
const enum radv_pipeline_type pipeline_type, bool consider_force_vrs,
|
||||
struct radv_shader_info *info);
|
||||
|
||||
void gfx10_get_ngg_info(const struct radv_device *device, struct radv_shader_info *es_info,
|
||||
struct radv_shader_info *gs_info, struct gfx10_ngg_info *out);
|
||||
|
||||
void radv_nir_shader_info_link(struct radv_device *device, const struct radv_graphics_state_key *gfx_state,
|
||||
struct radv_shader_stage *stages);
|
||||
|
||||
enum ac_hw_stage radv_select_hw_stage(const struct radv_shader_info *const info, const enum amd_gfx_level gfx_level);
|
||||
|
||||
#endif /* RADV_SHADER_INFO_H */
|
||||
Reference in New Issue
Block a user