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radv/gfx10: implement radv_pipeline_generate_geometry_shader()

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2019-06-25 13:25:32 +02:00
committed by Bas Nieuwenhuizen
parent 5551d6d6ea
commit b144a70ca8
1 changed files with 9 additions and 3 deletions
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6
src/amd/vulkan/radv_pipeline.c
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@@ -3210,9 +3210,15 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
va = radv_buffer_get_va(gs->bo) + gs->bo_offset; va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
radeon_emit(cs, va >> 8);
radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
} else {
radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2); radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
radeon_emit(cs, va >> 8); radeon_emit(cs, va >> 8);
radeon_emit(cs, S_00B214_MEM_BASE(va >> 40)); radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
}
radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
radeon_emit(cs, gs->config.rsrc1); radeon_emit(cs, gs->config.rsrc1);