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radv: INDEX_TYPE and NUM_INSTANCES PKT3 are not shadowed

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INDEX_TYPE and NUM_INSTANCES PKT3 should be always written
if shadowing is enabled since they are not shadowed.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18301>
This commit is contained in:
Yogesh Mohan Marimuthu
2022-09-12 23:31:11 +05:30
committed by Marge Bot
parent 2258090c73
commit b11f49f069
1 changed files with 4 additions and 2 deletions
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6
src/amd/vulkan/radv_cmd_buffer.c
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@@ -5272,7 +5272,8 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_d
disable_instance_packing = true;
}
if ((draw_info->indexed && state->index_type != state->last_index_type) ||
if ((draw_info->indexed &&
(state->index_type != state->last_index_type || cmd_buffer->device->uses_shadow_regs)) ||
(info->gfx_level == GFX10_3 &&
(state->last_index_type == -1 ||
disable_instance_packing != G_028A7C_DISABLE_INSTANCE_PACKING(state->last_index_type)))) {
@@ -8857,7 +8858,8 @@ radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info
struct radv_cmd_state *state = &cmd_buffer->state;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
assert(state->graphics_pipeline->vtx_base_sgpr);
if (state->last_num_instances != info->instance_count) {
if (state->last_num_instances != info->instance_count ||
cmd_buffer->device->uses_shadow_regs) {
radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
radeon_emit(cs, info->instance_count);
state->last_num_instances = info->instance_count;