OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

anv: Refactor anv_pipeline to use the anv_pipeline_type

Browse Source 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20316>
This commit is contained in:
Rohan Garg
2022-04-20 15:29:30 +02:00
committed by Marge Bot
parent ffc8d490b7
commit b1126abb38
5 changed files with 55 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/intel/vulkan/anv_genX.h
View File

@@ -85,7 +85,7 @@ void genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer);
enum anv_pipe_bits enum anv_pipe_bits
genX(emit_apply_pipe_flushes)(struct anv_batch *batch, genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
struct anv_device *device, struct anv_device *device,
uint32_t current_pipeline, enum anv_hw_pipeline_state current_pipeline,
enum anv_pipe_bits bits); enum anv_pipe_bits bits);
void genX(emit_so_memcpy_init)(struct anv_memcpy_state *state, void genX(emit_so_memcpy_init)(struct anv_memcpy_state *state,

26
src/intel/vulkan/anv_pipeline.c
View File

@@ -273,7 +273,7 @@ anv_shader_stage_to_nir(struct anv_device *device,
VkResult VkResult
anv_pipeline_init(struct anv_pipeline *pipeline, anv_pipeline_init(struct anv_pipeline *pipeline,
struct anv_device *device, struct anv_device *device,
enum anv_pipeline_type type, enum anv_hw_pipeline_state type,
VkPipelineCreateFlags flags, VkPipelineCreateFlags flags,
const VkAllocationCallbacks *pAllocator) const VkAllocationCallbacks *pAllocator)
{ {
@@ -330,7 +330,7 @@ void anv_DestroyPipeline(
return; return;
switch (pipeline->type) { switch (pipeline->type) {
case ANV_PIPELINE_GRAPHICS: { case ANV_HW_PIPELINE_STATE_GRAPHICS: {
struct anv_graphics_pipeline *gfx_pipeline = struct anv_graphics_pipeline *gfx_pipeline =
anv_pipeline_to_graphics(pipeline); anv_pipeline_to_graphics(pipeline);
@@ -341,7 +341,7 @@ void anv_DestroyPipeline(
break; break;
} }
case ANV_PIPELINE_COMPUTE: { case ANV_HW_PIPELINE_STATE_COMPUTE: {
struct anv_compute_pipeline *compute_pipeline = struct anv_compute_pipeline *compute_pipeline =
anv_pipeline_to_compute(pipeline); anv_pipeline_to_compute(pipeline);
@@ -351,7 +351,7 @@ void anv_DestroyPipeline(
break; break;
} }
case ANV_PIPELINE_RAY_TRACING: { case ANV_HW_PIPELINE_STATE_RAY_TRACING: {
struct anv_ray_tracing_pipeline *rt_pipeline = struct anv_ray_tracing_pipeline *rt_pipeline =
anv_pipeline_to_ray_tracing(pipeline); anv_pipeline_to_ray_tracing(pipeline);
@@ -849,7 +849,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
NIR_PASS(_, nir, anv_nir_lower_ycbcr_textures, layout); NIR_PASS(_, nir, anv_nir_lower_ycbcr_textures, layout);
if (pipeline->type == ANV_PIPELINE_GRAPHICS) { if (pipeline->type == ANV_HW_PIPELINE_STATE_GRAPHICS) {
struct anv_graphics_pipeline *gfx_pipeline = struct anv_graphics_pipeline *gfx_pipeline =
anv_pipeline_to_graphics(pipeline); anv_pipeline_to_graphics(pipeline);
NIR_PASS(_, nir, anv_nir_lower_multiview, gfx_pipeline->view_mask, NIR_PASS(_, nir, anv_nir_lower_multiview, gfx_pipeline->view_mask,
@@ -2137,7 +2137,7 @@ anv_compute_pipeline_create(struct anv_device *device,
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY); return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
result = anv_pipeline_init(&pipeline->base, device, result = anv_pipeline_init(&pipeline->base, device,
ANV_PIPELINE_COMPUTE, pCreateInfo->flags, ANV_HW_PIPELINE_STATE_COMPUTE, pCreateInfo->flags,
pAllocator); pAllocator);
if (result != VK_SUCCESS) { if (result != VK_SUCCESS) {
vk_free2(&device->vk.alloc, pAllocator, pipeline); vk_free2(&device->vk.alloc, pAllocator, pipeline);
@@ -2231,7 +2231,7 @@ anv_graphics_pipeline_init(struct anv_graphics_pipeline *pipeline,
VkResult result; VkResult result;
result = anv_pipeline_init(&pipeline->base, device, result = anv_pipeline_init(&pipeline->base, device,
ANV_PIPELINE_GRAPHICS, pCreateInfo->flags, ANV_HW_PIPELINE_STATE_GRAPHICS, pCreateInfo->flags,
alloc); alloc);
if (result != VK_SUCCESS) if (result != VK_SUCCESS)
return result; return result;
@@ -3079,7 +3079,7 @@ anv_ray_tracing_pipeline_create(
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY); return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
result = anv_pipeline_init(&pipeline->base, device, result = anv_pipeline_init(&pipeline->base, device,
ANV_PIPELINE_RAY_TRACING, pCreateInfo->flags, ANV_HW_PIPELINE_STATE_RAY_TRACING, pCreateInfo->flags,
pAllocator); pAllocator);
if (result != VK_SUCCESS) { if (result != VK_SUCCESS) {
vk_free2(&device->vk.alloc, pAllocator, pipeline); vk_free2(&device->vk.alloc, pAllocator, pipeline);
@@ -3286,15 +3286,15 @@ VkResult anv_GetPipelineExecutableStatisticsKHR(
const struct brw_stage_prog_data *prog_data; const struct brw_stage_prog_data *prog_data;
switch (pipeline->type) { switch (pipeline->type) {
case ANV_PIPELINE_GRAPHICS: { case ANV_HW_PIPELINE_STATE_GRAPHICS: {
prog_data = anv_pipeline_to_graphics(pipeline)->shaders[exe->stage]->prog_data; prog_data = anv_pipeline_to_graphics(pipeline)->shaders[exe->stage]->prog_data;
break; break;
} }
case ANV_PIPELINE_COMPUTE: { case ANV_HW_PIPELINE_STATE_COMPUTE: {
prog_data = anv_pipeline_to_compute(pipeline)->cs->prog_data; prog_data = anv_pipeline_to_compute(pipeline)->cs->prog_data;
break; break;
} }
case ANV_PIPELINE_RAY_TRACING: { case ANV_HW_PIPELINE_STATE_RAY_TRACING: {
struct anv_shader_bin **shader = struct anv_shader_bin **shader =
util_dynarray_element(&anv_pipeline_to_ray_tracing(pipeline)->shaders, util_dynarray_element(&anv_pipeline_to_ray_tracing(pipeline)->shaders,
struct anv_shader_bin *, struct anv_shader_bin *,
@@ -3463,7 +3463,7 @@ anv_GetRayTracingShaderGroupHandlesKHR(
ANV_FROM_HANDLE(anv_device, device, _device); ANV_FROM_HANDLE(anv_device, device, _device);
ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline); ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
if (pipeline->type != ANV_PIPELINE_RAY_TRACING) if (pipeline->type != ANV_HW_PIPELINE_STATE_RAY_TRACING)
return vk_error(device, VK_ERROR_FEATURE_NOT_PRESENT); return vk_error(device, VK_ERROR_FEATURE_NOT_PRESENT);
struct anv_ray_tracing_pipeline *rt_pipeline = struct anv_ray_tracing_pipeline *rt_pipeline =
@@ -3501,7 +3501,7 @@ anv_GetRayTracingShaderGroupStackSizeKHR(
VkShaderGroupShaderKHR groupShader) VkShaderGroupShaderKHR groupShader)
{ {
ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline); ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
assert(pipeline->type == ANV_PIPELINE_RAY_TRACING); assert(pipeline->type == ANV_HW_PIPELINE_STATE_RAY_TRACING);
struct anv_ray_tracing_pipeline *rt_pipeline = struct anv_ray_tracing_pipeline *rt_pipeline =
anv_pipeline_to_ray_tracing(pipeline); anv_pipeline_to_ray_tracing(pipeline);

25
src/intel/vulkan/anv_private.h
View File

@@ -2581,10 +2581,15 @@ struct anv_cmd_ray_tracing_state {
} scratch; } scratch;
}; };
enum anv_hw_pipeline_state {
ANV_HW_PIPELINE_STATE_GRAPHICS,
ANV_HW_PIPELINE_STATE_COMPUTE,
ANV_HW_PIPELINE_STATE_RAY_TRACING,
};
/** State required while building cmd buffer */ /** State required while building cmd buffer */
struct anv_cmd_state { struct anv_cmd_state {
/* PIPELINE_SELECT.PipelineSelection */ enum anv_hw_pipeline_state current_pipeline;
uint32_t current_pipeline;
const struct intel_l3_config * current_l3_config; const struct intel_l3_config * current_l3_config;
uint32_t last_aux_map_state; uint32_t last_aux_map_state;
@@ -2984,12 +2989,6 @@ struct anv_pipeline_executable {
char *disasm; char *disasm;
}; };
enum anv_pipeline_type {
ANV_PIPELINE_GRAPHICS,
ANV_PIPELINE_COMPUTE,
ANV_PIPELINE_RAY_TRACING,
};
struct anv_pipeline { struct anv_pipeline {
struct vk_object_base base; struct vk_object_base base;
@@ -3000,7 +2999,7 @@ struct anv_pipeline {
void * mem_ctx; void * mem_ctx;
enum anv_pipeline_type type; enum anv_hw_pipeline_state type;
VkPipelineCreateFlags flags; VkPipelineCreateFlags flags;
uint32_t ray_queries; uint32_t ray_queries;
@@ -3115,9 +3114,9 @@ struct anv_ray_tracing_pipeline {
return (struct anv_##pipe_type##_pipeline *) pipeline; \ return (struct anv_##pipe_type##_pipeline *) pipeline; \
} }
ANV_DECL_PIPELINE_DOWNCAST(graphics, ANV_PIPELINE_GRAPHICS) ANV_DECL_PIPELINE_DOWNCAST(graphics, ANV_HW_PIPELINE_STATE_GRAPHICS)
ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_PIPELINE_COMPUTE) ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_HW_PIPELINE_STATE_COMPUTE)
ANV_DECL_PIPELINE_DOWNCAST(ray_tracing, ANV_PIPELINE_RAY_TRACING) ANV_DECL_PIPELINE_DOWNCAST(ray_tracing, ANV_HW_PIPELINE_STATE_RAY_TRACING)
static inline bool static inline bool
anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline, anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline,
@@ -3206,7 +3205,7 @@ anv_device_finish_rt_shaders(struct anv_device *device);
VkResult VkResult
anv_pipeline_init(struct anv_pipeline *pipeline, anv_pipeline_init(struct anv_pipeline *pipeline,
struct anv_device *device, struct anv_device *device,
enum anv_pipeline_type type, enum anv_hw_pipeline_state type,
VkPipelineCreateFlags flags, VkPipelineCreateFlags flags,
const VkAllocationCallbacks *pAllocator); const VkAllocationCallbacks *pAllocator);

35
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -56,7 +56,7 @@
#include "genX_cmd_draw_helpers.h" #include "genX_cmd_draw_helpers.h"
static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
uint32_t pipeline); enum anv_hw_pipeline_state pipeline);
static enum anv_pipe_bits static enum anv_pipe_bits
convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) { convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
@@ -156,7 +156,8 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
* mode by putting the pipeline temporarily in 3D mode. * mode by putting the pipeline temporarily in 3D mode.
*/ */
uint32_t gfx12_wa_pipeline = cmd_buffer->state.current_pipeline; enum anv_hw_pipeline_state gfx12_wa_pipeline =
cmd_buffer->state.current_pipeline;
genX(flush_pipeline_select_3d)(cmd_buffer); genX(flush_pipeline_select_3d)(cmd_buffer);
#endif #endif
@@ -1517,7 +1518,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
ALWAYS_INLINE enum anv_pipe_bits ALWAYS_INLINE enum anv_pipe_bits
genX(emit_apply_pipe_flushes)(struct anv_batch *batch, genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
struct anv_device *device, struct anv_device *device,
uint32_t current_pipeline, enum anv_hw_pipeline_state current_pipeline,
enum anv_pipe_bits bits) enum anv_pipe_bits bits)
{ {
#if GFX_VER >= 12 #if GFX_VER >= 12
@@ -1618,7 +1619,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
* The same text exists a few rows below for Post Sync Op. * The same text exists a few rows below for Post Sync Op.
*/ */
if (bits & ANV_PIPE_POST_SYNC_BIT) { if (bits & ANV_PIPE_POST_SYNC_BIT) {
if (GFX_VER == 9 && current_pipeline == GPGPU) if (GFX_VER == 9 && current_pipeline == ANV_HW_PIPELINE_STATE_COMPUTE)
bits |= ANV_PIPE_CS_STALL_BIT; bits |= ANV_PIPE_CS_STALL_BIT;
bits &= ~ANV_PIPE_POST_SYNC_BIT; bits &= ~ANV_PIPE_POST_SYNC_BIT;
} }
@@ -6145,9 +6146,23 @@ genX(CmdTraceRaysIndirect2KHR)(
#endif /* GFX_VERx10 >= 125 */ #endif /* GFX_VERx10 >= 125 */
static uint32_t
anv_pipeline_selection_from_type(enum anv_hw_pipeline_state pipeline)
{
switch (pipeline) {
case ANV_HW_PIPELINE_STATE_GRAPHICS:
return _3D;
case ANV_HW_PIPELINE_STATE_COMPUTE:
case ANV_HW_PIPELINE_STATE_RAY_TRACING:
return GPGPU;
default:
unreachable("Unsupported pipeline");
}
}
static void static void
genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
uint32_t pipeline) enum anv_hw_pipeline_state pipeline)
{ {
UNUSED const struct intel_device_info *devinfo = cmd_buffer->device->info; UNUSED const struct intel_device_info *devinfo = cmd_buffer->device->info;
@@ -6164,10 +6179,10 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
* The internal hardware docs recommend the same workaround for Gfx9 * The internal hardware docs recommend the same workaround for Gfx9
* hardware too. * hardware too.
*/ */
if (pipeline == GPGPU) if (pipeline == ANV_HW_PIPELINE_STATE_COMPUTE)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t); anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
if (pipeline == _3D) { if (pipeline == ANV_HW_PIPELINE_STATE_GRAPHICS) {
/* There is a mid-object preemption workaround which requires you to /* There is a mid-object preemption workaround which requires you to
* re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However, * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
* even without preemption, we have issues with geometry flickering when * even without preemption, we have issues with geometry flickering when
@@ -6219,7 +6234,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) { anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3; ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12; ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
ps.PipelineSelection = pipeline; ps.PipelineSelection = anv_pipeline_selection_from_type(pipeline);
} }
#if GFX_VER == 9 #if GFX_VER == 9
@@ -6245,13 +6260,13 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
void void
genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer) genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
{ {
genX(flush_pipeline_select)(cmd_buffer, _3D); genX(flush_pipeline_select)(cmd_buffer, ANV_HW_PIPELINE_STATE_GRAPHICS);
} }
void void
genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer) genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer)
{ {
genX(flush_pipeline_select)(cmd_buffer, GPGPU); genX(flush_pipeline_select)(cmd_buffer, ANV_HW_PIPELINE_STATE_COMPUTE);
} }
void void

6
src/intel/vulkan/genX_gpu_memcpy.c
View File

@@ -252,7 +252,8 @@ genX(emit_so_memcpy_init)(struct anv_memcpy_state *state,
void void
genX(emit_so_memcpy_fini)(struct anv_memcpy_state *state) genX(emit_so_memcpy_fini)(struct anv_memcpy_state *state)
{ {
genX(emit_apply_pipe_flushes)(state->batch, state->device, _3D, genX(emit_apply_pipe_flushes)(state->batch, state->device,
ANV_HW_PIPELINE_STATE_GRAPHICS,
ANV_PIPE_END_OF_PIPE_SYNC_BIT); ANV_PIPE_END_OF_PIPE_SYNC_BIT);
anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end); anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end);
@@ -270,7 +271,8 @@ genX(emit_so_memcpy)(struct anv_memcpy_state *state,
anv_gfx8_9_vb_cache_range_needs_workaround(&state->vb_bound, anv_gfx8_9_vb_cache_range_needs_workaround(&state->vb_bound,
&state->vb_dirty, &state->vb_dirty,
src, size)) { src, size)) {
genX(emit_apply_pipe_flushes)(state->batch, state->device, _3D, genX(emit_apply_pipe_flushes)(state->batch, state->device,
ANV_HW_PIPELINE_STATE_GRAPHICS,
ANV_PIPE_CS_STALL_BIT | ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_VF_CACHE_INVALIDATE_BIT); ANV_PIPE_VF_CACHE_INVALIDATE_BIT);
memset(&state->vb_dirty, 0, sizeof(state->vb_dirty)); memset(&state->vb_dirty, 0, sizeof(state->vb_dirty));