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freedreno/ir3: Fix ldg decoding/parsing

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Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
This commit is contained in:
Rob Clark
2021-01-04 12:47:36 -08:00
committed by Marge Bot
parent a7e88787f6
commit b073dae5f0
3 changed files with 10 additions and 0 deletions
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3
src/freedreno/ir3/disasm-a3xx.c
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@@ -957,6 +957,9 @@ static void print_instr_cat6_a3xx(struct disasm_ctx *ctx, instr_t *instr)
fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1); fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
fprintf(ctx->out, ".%c", ss); fprintf(ctx->out, ".%c", ss);
break; break;
case OPC_LDG:
fprintf(ctx->out, ".%s", type[cat6->type]);
break;
default: default:
dst.im = cat6->g && !cat6->dst_off; dst.im = cat6->g && !cat6->dst_off;
if (dst.im) if (dst.im)

1
src/freedreno/ir3/ir3_parser.y
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@@ -905,6 +905,7 @@ cat6_dim: '.' T_1D { instr->cat6.d = 1; }
cat6_type: '.' type { instr->cat6.type = $2; } cat6_type: '.' type { instr->cat6.type = $2; }
cat6_offset: offset { new_reg(0, IR3_REG_IMMED)->iim_val = $1; } cat6_offset: offset { new_reg(0, IR3_REG_IMMED)->iim_val = $1; }
| '+' reg
cat6_dst_offset: offset { instr->cat6.dst_offset = $1; } cat6_dst_offset: offset { instr->cat6.dst_offset = $1; }
| '+' reg { instr->flags |= IR3_INSTR_G; } | '+' reg { instr->flags |= IR3_INSTR_G; }

6
src/freedreno/ir3/tests/disasm.c
View File

@@ -141,6 +141,12 @@ static const struct test {
INSTR_6XX(c0ca0500_03800042, "stg.s32 g[r0.z], r8.y, 3"), INSTR_6XX(c0ca0500_03800042, "stg.s32 g[r0.z], r8.y, 3"),
INSTR_6XX(c0ca0531_03800242, "stg.s32 g[r0.z+305], r8.y, 3"), INSTR_6XX(c0ca0531_03800242, "stg.s32 g[r0.z+305], r8.y, 3"),
INSTR_6XX(c0020011_04c08023, "ldg.f32 r4.y, g[r0.z+r4.y], 4"), /* ldg.a.f32 r4.y, g[r0.z+(r4.y<<2)], 4 */
INSTR_6XX(c0060006_01c18017, "ldg.u32 r1.z, g[r1.z+r2.w], 1"), /* ldg.a.u32 r1.z, g[r1.z+(r2.w<<2)], 1 */
INSTR_6XX(c0060006_0181800f, "ldg.u32 r1.z, g[r1.z+7], 1"),
INSTR_6XX(c0060006_01818001, "ldg.u32 r1.z, g[r1.z], 1"),
INSTR_6XX(c0060003_0180c269, "ldg.u32 r0.w, g[r0.w+308], 1"),
/* TODO: We don't support disasm of stc yet and produce a stgb instead /* TODO: We don't support disasm of stc yet and produce a stgb instead
* (same as their disasm does for other families. They're used as part * (same as their disasm does for other families. They're used as part
* uniforms setup, followed by a shpe and then a load of the constant that * uniforms setup, followed by a shpe and then a load of the constant that