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radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*

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The registers don't exist on GFX9.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2016-12-08 16:54:24 +01:00
parent de7967a27a
commit b054718218
1 changed files with 19 additions and 15 deletions
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34
src/gallium/drivers/radeonsi/si_state.c
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@@ -4081,24 +4081,28 @@ static void si_init_config(struct si_context *sctx)
raster_config_1 = 0x00000000; raster_config_1 = 0x00000000;
break; break;
default: default:
fprintf(stderr, if (sctx->b.chip_class <= VI) {
"radeonsi: Unknown GPU, using 0 for raster_config\n"); fprintf(stderr,
raster_config = 0x00000000; "radeonsi: Unknown GPU, using 0 for raster_config\n");
raster_config_1 = 0x00000000; raster_config = 0x00000000;
raster_config_1 = 0x00000000;
}
break; break;
} }
/* Always use the default config when all backends are enabled if (sctx->b.chip_class <= VI) {
* (or when we failed to determine the enabled backends). if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
*/ /* Always use the default config when all backends are enabled
if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { * (or when we failed to determine the enabled backends).
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, */
raster_config); si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
if (sctx->b.chip_class >= CIK) raster_config);
si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, if (sctx->b.chip_class >= CIK)
raster_config_1); si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
} else { raster_config_1);
si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1); } else {
si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
}
} }
si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));