diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 34562d4e273..0a90042239f 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -810,10 +810,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
               const struct vk_color_blend_state *cb,
               const struct vk_multisample_state *ms)
 {
-   struct GENX(BLEND_STATE) blend_state = {
-      .AlphaToCoverageEnable = ms && ms->alpha_to_coverage_enable,
-   };
-
    uint32_t surface_count = 0;
    struct anv_pipeline_bind_map *map;
    if (anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
@@ -821,8 +817,7 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
       surface_count = map->surface_count;
    }
 
-   uint32_t *blend_state_start = pipeline->gfx8.blend_state;
-   uint32_t *state_pos = blend_state_start;
+   uint32_t *state_pos = pipeline->gfx8.blend_state;
 
    state_pos += GENX(BLEND_STATE_length);
    for (unsigned i = 0; i < surface_count; i++) {
@@ -866,8 +861,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
       GENX(BLEND_STATE_ENTRY_pack)(NULL, state_pos, &entry);
       state_pos += GENX(BLEND_STATE_ENTRY_length);
    }
-
-   GENX(BLEND_STATE_pack)(NULL, blend_state_start, &blend_state);
 }
 
 static void
diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c
index f4a7f926015..60a9945e804 100644
--- a/src/intel/vulkan/gfx8_cmd_buffer.c
+++ b/src/intel/vulkan/gfx8_cmd_buffer.c
@@ -685,6 +685,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       memset(blend_dws, 0, sizeof(blend_dws));
 
       struct GENX(BLEND_STATE) blend_state = {
+         .AlphaToCoverageEnable = dyn->ms.alpha_to_coverage_enable,
          .AlphaToOneEnable = dyn->ms.alpha_to_one_enable,
       };