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i965: Remove duplicate brw_opcodes table in favor of opcode_descs.

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brw_optimize.c's brw_opcodes table was a copy of brw_disasm.c's
opcode_descs table, but with an additional field: is_arith.  Now that
I've deleted that, the two are identical.  Keep the one in brw_disasm.c.

Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke
2012-11-14 14:24:31 -08:00
parent a405717b88
commit b02492fd33
4 changed files with 4 additions and 65 deletions
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7
src/mesa/drivers/dri/i965/brw_context.h
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@@ -1076,13 +1076,6 @@ struct brw_context
int basevertex; int basevertex;
}; };
struct brw_instruction_info {
char *name;
int nsrc;
int ndst;
};
extern const struct brw_instruction_info brw_opcodes[128];
/*====================================================================== /*======================================================================
* brw_vtbl.c * brw_vtbl.c
*/ */

4
src/mesa/drivers/dri/i965/brw_fs_emit.cpp
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@@ -1006,9 +1006,9 @@ fs_visitor::generate_code()
break; break;
default: default:
if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
_mesa_problem(ctx, "Unsupported opcode `%s' in FS", _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
brw_opcodes[inst->opcode].name); opcode_descs[inst->opcode].name);
} else { } else {
_mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode); _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
} }

54
src/mesa/drivers/dri/i965/brw_optimize.c
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@@ -32,60 +32,6 @@
#include "brw_defines.h" #include "brw_defines.h"
#include "brw_eu.h" #include "brw_eu.h"
const struct brw_instruction_info brw_opcodes[128] = {
[BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
[BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
[BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
};
static bool static bool
is_single_channel_dp4(struct brw_instruction *insn) is_single_channel_dp4(struct brw_instruction *insn)
{ {

4
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
View File

@@ -763,9 +763,9 @@ vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
break; break;
default: default:
if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
fail("unsupported opcode in `%s' in VS\n", fail("unsupported opcode in `%s' in VS\n",
brw_opcodes[inst->opcode].name); opcode_descs[inst->opcode].name);
} else { } else {
fail("Unsupported opcode %d in VS", inst->opcode); fail("Unsupported opcode %d in VS", inst->opcode);
} }