intel/compiler/mesh: remove dead code path supporting >4 dword writes
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20858>
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@@ -927,7 +927,6 @@ emit_urb_direct_vec4_write(const fs_builder &bld,
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unsigned urb_global_offset,
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const fs_reg &src,
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fs_reg urb_handle,
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unsigned src_comp_offset,
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unsigned dst_comp_offset,
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unsigned comps,
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unsigned mask)
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@@ -942,7 +941,7 @@ emit_urb_direct_vec4_write(const fs_builder &bld,
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payload_srcs[length++] = reg_undef;
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for (unsigned c = 0; c < comps; c++)
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payload_srcs[length++] = quarter(offset(src, bld, c + src_comp_offset), q);
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payload_srcs[length++] = quarter(offset(src, bld, c), q);
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fs_reg srcs[URB_LOGICAL_NUM_SRCS];
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srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
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@@ -969,39 +968,23 @@ emit_urb_direct_writes(const fs_builder &bld, nir_intrinsic_instr *instr,
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assert(nir_src_is_const(*offset_nir_src));
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const unsigned comps = nir_src_num_components(instr->src[0]);
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assert(comps <= 8);
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assert(comps <= 4);
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const unsigned mask = nir_intrinsic_write_mask(instr);
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const unsigned offset_in_dwords = nir_intrinsic_base(instr) +
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nir_src_as_uint(*offset_nir_src) +
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component_from_intrinsic(instr);
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/* URB writes are vec4 aligned but the intrinsic offsets are in dwords.
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* With a max of 4 components, an intrinsic can require up to two writes.
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*
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* First URB write will be shifted by comp_shift. If there are other
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* components left, then dispatch a second write. In addition to that,
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* take mask into account to decide whether each write will be actually
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* needed.
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* We can write up to 8 dwords, so single vec4 write is enough.
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*/
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const unsigned comp_shift = offset_in_dwords % 4;
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const unsigned first_comps = MIN2(comps, 8 - comp_shift);
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const unsigned second_comps = comps - first_comps;
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const unsigned first_mask = (mask << comp_shift) & 0xFF;
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const unsigned second_mask = (mask >> (8 - comp_shift)) & 0xFF;
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const unsigned comp_shift = offset_in_dwords % 4;
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const unsigned mask = nir_intrinsic_write_mask(instr) << comp_shift;
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unsigned urb_global_offset = offset_in_dwords / 4;
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adjust_handle_and_offset(bld, urb_handle, urb_global_offset);
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if (first_mask > 0)
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emit_urb_direct_vec4_write(bld, urb_global_offset, src, urb_handle, 0, comp_shift, first_comps, first_mask);
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if (second_mask > 0) {
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urb_global_offset += 2;
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adjust_handle_and_offset(bld, urb_handle, urb_global_offset);
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emit_urb_direct_vec4_write(bld, urb_global_offset, src, urb_handle, first_comps, 0, second_comps, second_mask);
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}
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emit_urb_direct_vec4_write(bld, urb_global_offset, src, urb_handle,
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comp_shift, comps, mask);
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}
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static void
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@@ -1010,7 +993,6 @@ emit_urb_indirect_vec4_write(const fs_builder &bld,
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unsigned base,
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const fs_reg &src,
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fs_reg urb_handle,
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unsigned src_comp_offset,
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unsigned dst_comp_offset,
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unsigned comps,
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unsigned mask)
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@@ -1030,7 +1012,7 @@ emit_urb_indirect_vec4_write(const fs_builder &bld,
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payload_srcs[length++] = reg_undef;
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for (unsigned c = 0; c < comps; c++)
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payload_srcs[length++] = quarter(offset(src, bld, c + src_comp_offset), q);
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payload_srcs[length++] = quarter(offset(src, bld, c), q);
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fs_reg srcs[URB_LOGICAL_NUM_SRCS];
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srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
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@@ -1055,29 +1037,16 @@ emit_urb_indirect_writes_mod(const fs_builder &bld, nir_intrinsic_instr *instr,
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assert(nir_src_bit_size(instr->src[0]) == 32);
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const unsigned comps = nir_src_num_components(instr->src[0]);
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assert(comps <= 8);
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assert(comps <= 4);
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const unsigned mask = nir_intrinsic_write_mask(instr);
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const unsigned base_in_dwords = nir_intrinsic_base(instr) +
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component_from_intrinsic(instr);
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const unsigned comp_shift = mod;
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const unsigned first_comps = MIN2(comps, 8 - comp_shift);
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const unsigned second_comps = comps - first_comps;
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const unsigned first_mask = (mask << comp_shift) & 0xFF;
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const unsigned second_mask = (mask >> (8 - comp_shift)) & 0xFF;
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const unsigned comp_shift = mod;
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const unsigned mask = nir_intrinsic_write_mask(instr) << comp_shift;
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if (first_mask > 0) {
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emit_urb_indirect_vec4_write(bld, offset_src, base_in_dwords, src,
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urb_handle, 0, comp_shift, first_comps,
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first_mask);
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}
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if (second_mask > 0) {
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emit_urb_indirect_vec4_write(bld, offset_src, base_in_dwords + 8, src,
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urb_handle, first_comps, 0, second_comps,
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second_mask);
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}
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emit_urb_indirect_vec4_write(bld, offset_src, base_in_dwords, src,
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urb_handle, comp_shift, comps, mask);
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}
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static void
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@@ -1268,8 +1237,7 @@ fs_visitor::emit_task_mesh_store(const fs_builder &bld, nir_intrinsic_instr *ins
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if (offset_nir_src->is_ssa) {
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/* Try to calculate the value of (offset + base) % 4. If we can do
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* this, then we can do indirect writes using only up to 2 URB
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* writes (1 if modulo + num_comps is <= 4).
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* this, then we can do indirect writes using only 1 URB write.
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*/
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use_mod = nir_mod_analysis(nir_get_ssa_scalar(offset_nir_src->ssa, 0), nir_type_uint, 4, &mod);
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if (use_mod) {
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