iris: ensure stalling pipe control before fast clear

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 87149cc545 ("blorp: update and move fast clear PIPE_CONTROLs to drivers")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24718>
This commit is contained in:
Lionel Landwerlin
2023-08-16 11:28:24 +03:00
committed by Marge Bot
parent bd1d322107
commit aebe584586

View File

@@ -254,13 +254,13 @@ fast_clear_color(struct iris_context *ice,
* and again afterwards to ensure that the resolve is complete before we * and again afterwards to ensure that the resolve is complete before we
* do any more regular drawing. * do any more regular drawing.
*/ */
enum pipe_control_flags pc_flags = iris_emit_end_of_pipe_sync(batch, "fast clear: pre-flush",
PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_TILE_CACHE_FLUSH | PIPE_CONTROL_TILE_CACHE_FLUSH |
(devinfo->verx10 == 120 ? PIPE_CONTROL_DEPTH_STALL : 0) | (devinfo->verx10 == 120 ? PIPE_CONTROL_DEPTH_STALL : 0) |
(devinfo->verx10 == 125 ? PIPE_CONTROL_FLUSH_HDC | (devinfo->verx10 == 125 ? PIPE_CONTROL_FLUSH_HDC |
PIPE_CONTROL_DATA_CACHE_FLUSH : 0) | PIPE_CONTROL_DATA_CACHE_FLUSH : 0) |
PIPE_CONTROL_PSS_STALL_SYNC; PIPE_CONTROL_PSS_STALL_SYNC);
/* From the ICL PRMs, Volume 9: Render Engine, State Caching : /* From the ICL PRMs, Volume 9: Render Engine, State Caching :
* *
@@ -315,12 +315,11 @@ fast_clear_color(struct iris_context *ice,
* the clear color doesn´t change, we invalidate both caches always. * the clear color doesn´t change, we invalidate both caches always.
*/ */
if (devinfo->ver >= 11) { if (devinfo->ver >= 11) {
pc_flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE | iris_emit_pipe_control_flush(batch, "fast clear: pre-flush",
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; PIPE_CONTROL_STATE_CACHE_INVALIDATE |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
} }
iris_emit_pipe_control_flush(batch, "fast clear: pre-flush", pc_flags);
iris_batch_sync_region_start(batch); iris_batch_sync_region_start(batch);
/* If we reach this point, we need to fast clear to change the state to /* If we reach this point, we need to fast clear to change the state to