From aea48a4ff17cb9a5e5120f8cbf0c508f0287d16b Mon Sep 17 00:00:00 2001 From: Harri Nieminen Date: Wed, 12 Apr 2023 07:10:19 +0300 Subject: [PATCH] amd: fix typos MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Timur Kristóf Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_gpu_info.h | 2 +- src/amd/common/ac_nir_cull.c | 4 ++-- src/amd/common/ac_nir_lower_esgs_io_to_mem.c | 2 +- src/amd/common/ac_nir_lower_ngg.c | 6 +++--- src/amd/common/ac_nir_lower_ps.c | 6 +++--- src/amd/common/ac_rgp.c | 2 +- src/amd/common/ac_shader_util.c | 2 +- src/amd/common/ac_shadowed_regs.c | 2 +- src/amd/common/ac_surface.c | 2 +- src/amd/compiler/README-ISA.md | 2 +- src/amd/compiler/README.md | 4 ++-- src/amd/compiler/aco_instruction_selection.cpp | 4 ++-- src/amd/compiler/aco_ir.h | 4 ++-- src/amd/compiler/aco_lower_to_hw_instr.cpp | 4 ++-- src/amd/compiler/aco_opcodes.py | 2 +- src/amd/compiler/aco_optimizer.cpp | 4 ++-- src/amd/compiler/aco_scheduler.cpp | 2 +- src/amd/compiler/aco_spill.cpp | 10 +++++----- src/amd/compiler/aco_util.h | 2 +- src/amd/drm-shim/README.md | 2 +- src/amd/llvm/ac_llvm_build.c | 4 ++-- src/amd/llvm/ac_nir_to_llvm.c | 2 +- src/amd/vulkan/bvh/ploc_internal.comp | 2 +- src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c | 2 +- src/amd/vulkan/radix_sort/radix_sort_vk.h | 16 ++++++++-------- src/amd/vulkan/radv_descriptor_set.c | 2 +- src/amd/vulkan/radv_llvm_helper.cpp | 2 +- src/amd/vulkan/radv_physical_device.c | 6 +++--- src/amd/vulkan/radv_pipeline_graphics.c | 2 +- src/amd/vulkan/radv_private.h | 2 +- src/amd/vulkan/radv_query.c | 2 +- src/amd/vulkan/radv_rra.c | 2 +- src/amd/vulkan/radv_rt_common.c | 4 ++-- src/amd/vulkan/radv_shader.c | 2 +- src/amd/vulkan/radv_sqtt.c | 2 +- 35 files changed, 60 insertions(+), 60 deletions(-) diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 72dc4d0dfb6..13f8d87f8d6 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -309,7 +309,7 @@ void ac_get_hs_info(struct radeon_info *info, * store the task payload which is passed to mesh shaders. * * The driver only needs to create this BO once, - * and it will always be able to accomodate the maximum needed + * and it will always be able to accommodate the maximum needed * task payload size. * * The following memory layout is used: diff --git a/src/amd/common/ac_nir_cull.c b/src/amd/common/ac_nir_cull.c index 1994c73c565..eb8a76deca4 100644 --- a/src/amd/common/ac_nir_cull.c +++ b/src/amd/common/ac_nir_cull.c @@ -241,7 +241,7 @@ cull_small_primitive_line(nir_builder *b, nir_ssa_def *pos[3][4], * it doesn't exit it. If a line is entirely inside a corner diamond, it can be culled * because it doesn't enter any diamond and thus can't exit any diamond. * - * The viewport is rotated by 45 degress to turn diamonds into squares, and a bounding + * The viewport is rotated by 45 degrees to turn diamonds into squares, and a bounding * box test is used to determine whether a line is entirely inside any square (diamond). * * The line width doesn't matter. Wide lines only duplicate filled pixels in either X or @@ -264,7 +264,7 @@ cull_small_primitive_line(nir_builder *b, nir_ssa_def *pos[3][4], v1[chan] = nir_ffma(b, pos[1][chan], vp_scale, vp_translate); } - /* Rotate the viewport by 45 degress, so that diamonds become squares. */ + /* Rotate the viewport by 45 degrees, so that diamonds become squares. */ rotate_45degrees(b, v0); rotate_45degrees(b, v1); diff --git a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c index 3208eeb9b19..bb490d5f391 100644 --- a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c @@ -62,7 +62,7 @@ emit_split_buffer_load(nir_builder *b, nir_ssa_def *desc, nir_ssa_def *v_off, ni unsigned full_dwords = total_bytes / 4u; unsigned remaining_bytes = total_bytes - full_dwords * 4u; - /* Accomodate max number of split 64-bit loads */ + /* Accommodate max number of split 64-bit loads */ nir_ssa_def *comps[NIR_MAX_VEC_COMPONENTS * 2u]; /* Assume that 1x32-bit load is better than 1x16-bit + 1x8-bit */ diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c index 27d9ca4e5c8..9ae0983ccf3 100644 --- a/src/amd/common/ac_nir_lower_ngg.c +++ b/src/amd/common/ac_nir_lower_ngg.c @@ -1494,7 +1494,7 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c /* Run culling algorithms if culling is enabled. * * NGG culling can be enabled or disabled in runtime. - * This is determined by a SGPR shader argument which is acccessed + * This is determined by a SGPR shader argument which is accessed * by the following NIR intrinsic. */ @@ -3233,7 +3233,7 @@ ngg_gs_build_streamout(nir_builder *b, lower_ngg_gs_state *s) /* We want to export primitives to streamout buffer in sequence, * but not all vertices are alive or mark end of a primitive, so - * there're "holes". We don't need continous invocations to write + * there're "holes". We don't need continuous invocations to write * primitives to streamout buffer like final vertex export, so * just repack to get the sequence (export_seq) is enough, no need * to do compaction. @@ -4018,7 +4018,7 @@ ms_emit_arrayed_outputs(nir_builder *b, nir_ssa_def *zero = nir_imm_int(b, 0); u_foreach_bit64(slot, mask) { - /* Should not occour here, handled separately. */ + /* Should not occur here, handled separately. */ assert(slot != VARYING_SLOT_PRIMITIVE_COUNT && slot != VARYING_SLOT_PRIMITIVE_INDICES); unsigned component_mask = s->output_info[slot].components_mask; diff --git a/src/amd/common/ac_nir_lower_ps.c b/src/amd/common/ac_nir_lower_ps.c index 53dbe486b11..5817d9f26b5 100644 --- a/src/amd/common/ac_nir_lower_ps.c +++ b/src/amd/common/ac_nir_lower_ps.c @@ -151,8 +151,8 @@ emit_ps_mrtz_export(nir_builder *b, lower_ps_state *s) uint64_t outputs_written = b->shader->info.outputs_written; /* use outputs_written to determine export format as we use it to set - * R_028710_SPI_SHADER_Z_FORMAT instead of relying on the real store ouput, - * because store ouput may be optimized out. + * R_028710_SPI_SHADER_Z_FORMAT instead of relying on the real store output, + * because store output may be optimized out. */ unsigned format = ac_get_spi_shader_z_format(outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH), @@ -352,7 +352,7 @@ emit_ps_color_export(nir_builder *b, lower_ps_state *s, gl_frag_result slot, uns pack_op = nir_op_pack_snorm_2x16; break; default: - unreachable("unsupport color export format"); + unreachable("unsupported color export format"); break; } diff --git a/src/amd/common/ac_rgp.c b/src/amd/common/ac_rgp.c index fa9ecb86d0c..6271444e453 100644 --- a/src/amd/common/ac_rgp.c +++ b/src/amd/common/ac_rgp.c @@ -192,7 +192,7 @@ static void ac_sqtt_fill_cpu_info(struct sqtt_file_chunk_cpu_info *chunk) if (os_get_total_physical_memory(&system_ram_size)) chunk->system_ram_size = system_ram_size / (1024 * 1024); - /* Parse cpuinfo to get more detailled information. */ + /* Parse cpuinfo to get more detailed information. */ f = fopen("/proc/cpuinfo", "r"); if (!f) return; diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c index 340d51f433c..29015ec271e 100644 --- a/src/amd/common/ac_shader_util.c +++ b/src/amd/common/ac_shader_util.c @@ -364,7 +364,7 @@ unsigned ac_get_tbuffer_format(enum amd_gfx_level gfx_level, unsigned dfmt, unsi // Use the regularity properties of the combined format enum. // // Note: float is incompatible with 8-bit data formats, - // [us]{norm,scaled} are incomparible with 32-bit data formats. + // [us]{norm,scaled} are incompatible with 32-bit data formats. // [us]scaled are not writable. switch (nfmt) { case V_008F0C_BUF_NUM_FORMAT_UNORM: diff --git a/src/amd/common/ac_shadowed_regs.c b/src/amd/common/ac_shadowed_regs.c index 1bc9d86e00d..f060d55cb64 100644 --- a/src/amd/common/ac_shadowed_regs.c +++ b/src/amd/common/ac_shadowed_regs.c @@ -4073,7 +4073,7 @@ void ac_check_shadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family fam unsigned end_reg_offset = reg_offset + count * 4; unsigned end_range_offset = ranges[i].offset + ranges[i].size; - /* Test if the ranges interect. */ + /* Test if the ranges intersect. */ if (MAX2(ranges[i].offset, reg_offset) < MIN2(end_range_offset, end_reg_offset)) { /* Assertion: A register can be listed only once. */ assert(!found); diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 024013d6cd9..430a68a7a6f 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -793,7 +793,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config * if (ret == ADDR_OK) { /* If the DCC memory isn't properly * aligned, the data are interleaved - * accross slices. + * across slices. */ if (AddrDccOut->dccRamSizeAligned) dcc_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize; diff --git a/src/amd/compiler/README-ISA.md b/src/amd/compiler/README-ISA.md index 3b8590cbe9b..8139d7e6876 100644 --- a/src/amd/compiler/README-ISA.md +++ b/src/amd/compiler/README-ISA.md @@ -327,7 +327,7 @@ Waiting for the VMEM/DS instruction to finish, a VALU or export instruction, or ### VALUTransUseHazard Triggered by: -A VALU instrction reading a VGPR written by a transcendental VALU instruction without 6+ VALU or 2+ +A VALU instruction reading a VGPR written by a transcendental VALU instruction without 6+ VALU or 2+ transcendental instructions in-between. Mitigated by: diff --git a/src/amd/compiler/README.md b/src/amd/compiler/README.md index 240cc69015f..774a52ce7ea 100644 --- a/src/amd/compiler/README.md +++ b/src/amd/compiler/README.md @@ -105,7 +105,7 @@ This means that we need to insert `s_waitcnt` instructions (and its variants) so #### Resolve hazards and insert NOPs Some instructions require wait states or other instructions to resolve hazards which are not handled by the hardware. -This pass makes sure that no known hazards occour. +This pass makes sure that no known hazards occur. #### Emit program - Assembler @@ -118,7 +118,7 @@ Which software stage gets executed on which hardware stage depends on what kind An important difference is that VS is always the first stage to run in SW models, whereas HW VS refers to the last HW stage before fragment shading in GCN/RDNA terminology. -That's why, among other things, the HW VS is no longer used to execute the SW VS when tesselation or geometry shading are used. +That's why, among other things, the HW VS is no longer used to execute the SW VS when tessellation or geometry shading are used. #### Glossary of software stages diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index d58bdbb6eaa..4ecfee98b06 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -786,7 +786,7 @@ get_alu_src_vop3p(struct isel_context* ctx, nir_alu_src src) /* extract a full dword if possible */ if (tmp.bytes() >= (dword + 1) * 4) { - /* if the source is splitted into components, use p_create_vector */ + /* if the source is split into components, use p_create_vector */ auto it = ctx->allocated_vec.find(tmp.id()); if (it != ctx->allocated_vec.end()) { unsigned index = dword << 1; @@ -5549,7 +5549,7 @@ mtbuf_load_callback(Builder& bld, const LoadEmitInfo& info, Temp offset, unsigne ac_get_safe_fetch_size(bld.program->gfx_level, vtx_info, const_offset, max_components, alignment, max_fetched_components); const unsigned fetch_fmt = vtx_info->hw_format[max_fetched_components - 1]; - /* Adjust bytes needed in case we need to do a smaller load due to aligment. + /* Adjust bytes needed in case we need to do a smaller load due to alignment. * If a larger format is selected, it's still OK to load a smaller amount from it. */ bytes_needed = MIN2(bytes_needed, max_fetched_components * info.component_size); diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index a282dc5c762..3fffffde459 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -2037,11 +2037,11 @@ static constexpr Stage vertex_geometry_gs(HWStage::GS, SWStage::VS_GS); static constexpr Stage vertex_tess_control_hs(HWStage::HS, SWStage::VS_TCS); static constexpr Stage tess_eval_geometry_gs(HWStage::GS, SWStage::TES_GS); /* pre-GFX9 */ -static constexpr Stage vertex_ls(HWStage::LS, SWStage::VS); /* vertex before tesselation control */ +static constexpr Stage vertex_ls(HWStage::LS, SWStage::VS); /* vertex before tessellation control */ static constexpr Stage vertex_es(HWStage::ES, SWStage::VS); /* vertex before geometry */ static constexpr Stage tess_control_hs(HWStage::HS, SWStage::TCS); static constexpr Stage tess_eval_es(HWStage::ES, - SWStage::TES); /* tesselation evaluation before geometry */ + SWStage::TES); /* tessellation evaluation before geometry */ static constexpr Stage geometry_gs(HWStage::GS, SWStage::GS); /* Raytracing */ static constexpr Stage raytracing_cs(HWStage::CS, SWStage::RT); diff --git a/src/amd/compiler/aco_lower_to_hw_instr.cpp b/src/amd/compiler/aco_lower_to_hw_instr.cpp index 6f82879fb1b..19e8ec70609 100644 --- a/src/amd/compiler/aco_lower_to_hw_instr.cpp +++ b/src/amd/compiler/aco_lower_to_hw_instr.cpp @@ -71,7 +71,7 @@ aco_opcode get_reduce_opcode(amd_gfx_level gfx_level, ReduceOp op) { /* Because some 16-bit instructions are already VOP3 on GFX10, we use the - * 32-bit opcodes (VOP2) which allows to remove the tempory VGPR and to use + * 32-bit opcodes (VOP2) which allows to remove the temporary VGPR and to use * DPP with the arithmetic instructions. This requires to sign-extend. */ switch (op) { @@ -718,7 +718,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c for (unsigned i = 0; i < src.size(); i++) { if (!identity[i].isConstant() || - identity[i].constantValue()) { /* bound_ctrl should take care of this overwise */ + identity[i].constantValue()) { /* bound_ctrl should take care of this otherwise */ if (ctx->program->gfx_level < GFX10) assert((identity[i].isConstant() && !identity[i].isLiteral()) || identity[i].physReg() == PhysReg{sitmp + i}); diff --git a/src/amd/compiler/aco_opcodes.py b/src/amd/compiler/aco_opcodes.py index 3f1fcd2d781..79e0033afab 100644 --- a/src/amd/compiler/aco_opcodes.py +++ b/src/amd/compiler/aco_opcodes.py @@ -205,7 +205,7 @@ class Opcode(object): - name is the name of the opcode (prepend nir_op_ for the enum name) - all types are strings that get nir_type_ prepended to them - input_types is a list of types - - algebraic_properties is a space-seperated string, where nir_op_is_ is + - algebraic_properties is a space-separated string, where nir_op_is_ is prepended before each entry - const_expr is an expression or series of statements that computes the constant value of the opcode given the constant values of its inputs. diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index cb318572599..c366feeba9f 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -1135,7 +1135,7 @@ apply_extract(opt_ctx& ctx, aco_ptr& instr, unsigned idx, ssa_info& sel.offset() == 0 && ((sel.size() == 2 && instr->operands[0].constantValue() >= 16u) || (sel.size() == 1 && instr->operands[0].constantValue() >= 24u))) { - /* The undesireable upper bits are already shifted out. */ + /* The undesirable upper bits are already shifted out. */ return; } else if (instr->opcode == aco_opcode::v_mul_u32_u24 && ctx.program->gfx_level >= GFX10 && !instr->usesModifiers() && sel.size() == 2 && !sel.sign_extend() && @@ -3567,7 +3567,7 @@ apply_ds_extract(opt_ctx& ctx, aco_ptr& extract) unsigned sign_ext = extract->operands[3].constantValue(); unsigned dst_bitsize = extract->definitions[0].bytes() * 8u; - /* TODO: These are doable, but probably don't occour too often. */ + /* TODO: These are doable, but probably don't occur too often. */ if (extract_idx || sign_ext || dst_bitsize != 32) return false; diff --git a/src/amd/compiler/aco_scheduler.cpp b/src/amd/compiler/aco_scheduler.cpp index 4ab13fe7c30..94429b34393 100644 --- a/src/amd/compiler/aco_scheduler.cpp +++ b/src/amd/compiler/aco_scheduler.cpp @@ -694,7 +694,7 @@ schedule_SMEM(sched_ctx& ctx, Block* block, std::vector& registe break; /* don't use LDS/GDS instructions to hide latency since it can - * significanly worsen LDS scheduling */ + * significantly worsen LDS scheduling */ if (candidate->isDS() || !can_move_down) { add_to_hazard_query(&hq, candidate.get()); ctx.mv.downwards_skip(cursor); diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp index ca97f748f5e..d2cbca24405 100644 --- a/src/amd/compiler/aco_spill.cpp +++ b/src/amd/compiler/aco_spill.cpp @@ -881,7 +881,7 @@ add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) Temp var = phi->operands[i].getTemp(); std::map::iterator rename_it = ctx.renames[pred_idx].find(var); - /* prevent the definining instruction from being DCE'd if it could be rematerialized */ + /* prevent the defining instruction from being DCE'd if it could be rematerialized */ if (rename_it == ctx.renames[preds[i]].end() && ctx.remat.count(var)) ctx.unused_remats.erase(ctx.remat[var].instr); @@ -1001,7 +1001,7 @@ add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) ctx.renames[pred_idx].find(phi->operands[i].getTemp()); if (it != ctx.renames[pred_idx].end()) { phi->operands[i].setTemp(it->second); - /* prevent the definining instruction from being DCE'd if it could be rematerialized */ + /* prevent the defining instruction from being DCE'd if it could be rematerialized */ } else { auto remat_it = ctx.remat.find(phi->operands[i].getTemp()); if (remat_it != ctx.remat.end()) { @@ -1117,7 +1117,7 @@ add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) tmp = rename; } else { tmp = pair.first; - /* prevent the definining instruction from being DCE'd if it could be rematerialized */ + /* prevent the defining instruction from being DCE'd if it could be rematerialized */ if (ctx.remat.count(tmp)) ctx.unused_remats.erase(ctx.remat[tmp].instr); } @@ -1162,7 +1162,7 @@ process_block(spill_ctx& ctx, unsigned block_idx, Block* block, RegisterDemand s std::vector> instructions; unsigned idx = 0; - /* phis are handled separetely */ + /* phis are handled separately */ while (block->instructions[idx]->opcode == aco_opcode::p_phi || block->instructions[idx]->opcode == aco_opcode::p_linear_phi) { instructions.emplace_back(std::move(block->instructions[idx++])); @@ -1191,7 +1191,7 @@ process_block(spill_ctx& ctx, unsigned block_idx, Block* block, RegisterDemand s if (rename_it != ctx.renames[block_idx].end()) { op.setTemp(rename_it->second); } else { - /* prevent its definining instruction from being DCE'd if it could be rematerialized */ + /* prevent its defining instruction from being DCE'd if it could be rematerialized */ auto remat_it = ctx.remat.find(op.getTemp()); if (remat_it != ctx.remat.end()) { ctx.unused_remats.erase(remat_it->second.instr); diff --git a/src/amd/compiler/aco_util.h b/src/amd/compiler/aco_util.h index ce29c0f7ac8..5f9630f2dd1 100644 --- a/src/amd/compiler/aco_util.h +++ b/src/amd/compiler/aco_util.h @@ -459,7 +459,7 @@ public: free(buffer); } - /* Delete copy-constructor and -assigment to avoid double free() */ + /* Delete copy-constructor and -assignment to avoid double free() */ monotonic_buffer_resource(const monotonic_buffer_resource&) = delete; monotonic_buffer_resource& operator=(const monotonic_buffer_resource&) = delete; diff --git a/src/amd/drm-shim/README.md b/src/amd/drm-shim/README.md index 9a41849b9ed..966e249adc9 100644 --- a/src/amd/drm-shim/README.md +++ b/src/amd/drm-shim/README.md @@ -6,5 +6,5 @@ The submit ioctl is stubbed out to not execute anything. Export `MESA_LOADER_DRIVER_OVERRIDE=r300 LD_PRELOAD=$prefix/lib/libradeon_noop_drm_shim.so`. (or r600 for r600-class HW) -By default, rv515 is exposed. The chip can be selected an enviornment +By default, rv515 is exposed. The chip can be selected an environment variable like `RADEON_GPU_ID=CAYMAN` or `RADEON_GPU_ID=0x6740`. diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c index dde69a0aa4a..c8ad9a51e07 100644 --- a/src/amd/llvm/ac_llvm_build.c +++ b/src/amd/llvm/ac_llvm_build.c @@ -872,7 +872,7 @@ void ac_prepare_cube_coords(struct ac_llvm_context *ctx, bool is_deriv, bool is_ * * where d is the depth of the texture array and layer * comes from the component indicated in the tables below. - * Workaroudn for an issue where the layer is taken from a + * Workaround for an issue where the layer is taken from a * helper invocation which happens to fall on a different * layer due to extrapolation." * @@ -1972,7 +1972,7 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx, struct ac_image_ if (atomic) { data_type = LLVMTypeOf(a->data[0]); } else if (a->opcode == ac_image_store || a->opcode == ac_image_store_mip) { - /* Image stores might have been shrinked using the format. */ + /* Image stores might have been shrunk using the format. */ data_type = LLVMTypeOf(a->data[0]); dmask = (1 << ac_get_llvm_num_components(a->data[0])) - 1; } else { diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index e464a55457e..a38e5d60d16 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -450,7 +450,7 @@ struct waterfall_context { * to implement the body. * * params: - * - ctx is the usal nir context + * - ctx is the usual nir context * - wctx is a temporary struct containing some loop info. Can be left uninitialized. * - value is the possibly divergent value for which we built the loop * - divergent is whether value is actually divergent. If false we just pass diff --git a/src/amd/vulkan/bvh/ploc_internal.comp b/src/amd/vulkan/bvh/ploc_internal.comp index d51706ed06d..253f26200ae 100644 --- a/src/amd/vulkan/bvh/ploc_internal.comp +++ b/src/amd/vulkan/bvh/ploc_internal.comp @@ -218,7 +218,7 @@ combined_node_cost(uint32_t lds_base, uint32_t i, uint32_t j) * tree depth for internal nodes) * * Dividing area by both relative costs will make it more likely that we merge nodes with - * a hight child cost. + * a high child cost. */ float p_i = aabb_surface_area(shared_bounds[i - lds_base]) / area; float p_j = aabb_surface_area(shared_bounds[j - lds_base]) / area; diff --git a/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c b/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c index 282ee237b96..f3022259d5f 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c +++ b/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c @@ -356,7 +356,7 @@ lower_load_vs_input(nir_builder *b, nir_intrinsic_instr *intrin, lower_vs_inputs nir_ssa_def *load = loads[0]; /* Extract the channels we actually need when we couldn't skip starting - * components or had to emit more than one load instrinsic. + * components or had to emit more than one load intrinsic. */ if (num_loads > 0 && (first_used_channel > skipped_start || num_loads != 1)) load = nir_extract_bits(b, loads, num_loads, (first_used_channel - skipped_start) * bit_size, diff --git a/src/amd/vulkan/radix_sort/radix_sort_vk.h b/src/amd/vulkan/radix_sort/radix_sort_vk.h index a1416ef133f..f52020880a8 100644 --- a/src/amd/vulkan/radix_sort/radix_sort_vk.h +++ b/src/amd/vulkan/radix_sort/radix_sort_vk.h @@ -198,19 +198,19 @@ radix_sort_vk_destroy(radix_sort_vk_t * rs, // // must be honored. All alignments are power of 2. // // Input: -// count : Maximum number of keyvals +// count : Maximum number of keyvals // // Outputs: -// keyval_size : Size of a single keyval +// keyval_size : Size of a single keyval // -// keyvals_size : Minimum size of the even and odd keyval buffers -// keyvals_alignment : Alignment of each keyval buffer +// keyvals_size : Minimum size of the even and odd keyval buffers +// keyvals_alignment : Alignment of each keyval buffer // -// internal_size : Minimum size of internal buffer -// internal_aligment : Alignment of the internal buffer +// internal_size : Minimum size of internal buffer +// internal_alignment : Alignment of the internal buffer // -// indirect_size : Minimum size of indirect buffer -// indirect_aligment : Alignment of the indirect buffer +// indirect_size : Minimum size of indirect buffer +// indirect_alignment : Alignment of the indirect buffer // // .keyvals_even/odd // ----------------- diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index c35cec10438..c8db0338044 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -174,7 +174,7 @@ radv_CreateDescriptorSetLayout(VkDevice _device, const VkDescriptorSetLayoutCrea size += ycbcr_sampler_count * sizeof(struct vk_ycbcr_conversion_state); } - /* We need to allocate decriptor set layouts off the device allocator with DEVICE scope because + /* We need to allocate descriptor set layouts off the device allocator with DEVICE scope because * they are reference counted and may not be destroyed when vkDestroyDescriptorSetLayout is * called. */ diff --git a/src/amd/vulkan/radv_llvm_helper.cpp b/src/amd/vulkan/radv_llvm_helper.cpp index 0341bfcc41f..0fedf5f58dd 100644 --- a/src/amd/vulkan/radv_llvm_helper.cpp +++ b/src/amd/vulkan/radv_llvm_helper.cpp @@ -70,7 +70,7 @@ class radv_llvm_per_thread_info { struct ac_compiler_passes *passes; }; -/* we have to store a linked list per thread due to the possiblity of multiple gpus being required */ +/* we have to store a linked list per thread due to the possibility of multiple gpus being required */ static thread_local std::list radv_llvm_per_thread_list; bool diff --git a/src/amd/vulkan/radv_physical_device.c b/src/amd/vulkan/radv_physical_device.c index b7e3803a1a5..53fb6cf3c86 100644 --- a/src/amd/vulkan/radv_physical_device.c +++ b/src/amd/vulkan/radv_physical_device.c @@ -2315,7 +2315,7 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32) device->cs_wave_size = 32; - /* For pixel shaders, wave64 is recommanded. */ + /* For pixel shaders, wave64 is recommended. */ if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32) device->ps_wave_size = 32; @@ -2641,7 +2641,7 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice, device->ws->query_value(device->ws, RADEON_GTT_USAGE); uint64_t total_usage = MAX2(total_internal_usage, total_system_usage); - /* Compute the total free space that can be allocated for this process accross all heaps. */ + /* Compute the total free space that can be allocated for this process across all heaps. */ uint64_t total_free_space = total_heap_size - MIN2(total_heap_size, total_usage); memoryBudget->heapBudget[vram_vis_heap_idx] = total_free_space + total_internal_usage; @@ -2673,7 +2673,7 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice, uint64_t total_usage = MAX2(total_internal_usage, total_system_usage); - /* Compute the total free space that can be allocated for this process accross all heaps. */ + /* Compute the total free space that can be allocated for this process across all heaps. */ uint64_t total_free_space = total_heap_size - MIN2(total_heap_size, total_usage); /* Compute the remaining visible VRAM size for this process. */ diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 36027d0368c..db5a51608e4 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -4106,7 +4106,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv if (enable_mrt_compaction) { blend.spi_shader_col_format = radv_compact_spi_shader_col_format(ps, &blend); - /* In presense of MRT holes (ie. the FS exports MRT1 but not MRT0), the compiler will remap + /* In presence of MRT holes (ie. the FS exports MRT1 but not MRT0), the compiler will remap * them, so that only MRT0 is exported and the driver will compact SPI_SHADER_COL_FORMAT to * match what the FS actually exports. Though, to make sure the hw remapping works as * expected, we should also clear color attachments without exports in CB_SHADER_MASK. diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 12de11d288d..f0fea917c91 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1789,7 +1789,7 @@ struct radv_cmd_buffer { } ace_internal; /** - * Whether a query pool has been resetted and we have to flush caches. + * Whether a query pool has been reset and we have to flush caches. */ bool pending_reset_query; diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index e084323b872..ffdbdb85022 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1466,7 +1466,7 @@ emit_query_flush(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo if (cmd_buffer->pending_reset_query) { if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) { /* Only need to flush caches if the query pool size is - * large enough to be resetted using the compute shader + * large enough to be reset using the compute shader * path. Small pools don't need any cache flushes * because we use a CP dma clear. */ diff --git a/src/amd/vulkan/radv_rra.c b/src/amd/vulkan/radv_rra.c index 1e6ef199421..0c7808d6de6 100644 --- a/src/amd/vulkan/radv_rra.c +++ b/src/amd/vulkan/radv_rra.c @@ -1242,7 +1242,7 @@ radv_rra_dump_trace(VkQueue vk_queue, char *filename) rra_dump_chunk_description(accel_struct_offsets[i], sizeof(struct rra_accel_struct_chunk_header), accel_struct_size, - "RawAccelStruc", RADV_RRA_CHUNK_ID_ACCEL_STRUCT, file); + "RawAccelStruct", RADV_RRA_CHUNK_ID_ACCEL_STRUCT, file); } uint64_t file_end = (uint64_t)ftell(file); diff --git a/src/amd/vulkan/radv_rt_common.c b/src/amd/vulkan/radv_rt_common.c index 82785a30010..2a663044419 100644 --- a/src/amd/vulkan/radv_rt_common.c +++ b/src/amd/vulkan/radv_rt_common.c @@ -108,7 +108,7 @@ intersect_ray_amd_software_box(struct radv_device *device, nir_builder *b, nir_s nir_store_var(b, child_indices, nir_imm_ivec4(b, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu), 0xf); - /* Need to remove infinities here because otherwise we get nasty NaN propogation + /* Need to remove infinities here because otherwise we get nasty NaN propagation * if the direction has 0s in it. */ /* inv_dir = clamp(inv_dir, -FLT_MAX, FLT_MAX); */ inv_dir = nir_fclamp(b, inv_dir, nir_imm_float(b, -FLT_MAX), nir_imm_float(b, FLT_MAX)); @@ -238,7 +238,7 @@ intersect_ray_amd_software_tri(struct radv_device *device, nir_builder *b, nir_s nir_ssa_def *k_indices[3] = {kx, ky, kz}; nir_ssa_def *k = nir_vec(b, k_indices, 3); - /* Swap kx and ky dimensions to preseve winding order */ + /* Swap kx and ky dimensions to preserve winding order */ unsigned swap_xy_swizzle[4] = {1, 0, 2, 3}; k = nir_bcsel(b, nir_flt(b, nir_vector_extract(b, dir, kz), nir_imm_float(b, 0.0f)), nir_swizzle(b, k, swap_xy_swizzle, 3), k); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 0129516cee5..c57e79c2ccb 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -2080,7 +2080,7 @@ radv_aco_build_shader_binary(void **bin, const struct ac_shader_config *config, size += code_dw * sizeof(uint32_t) + sizeof(struct radv_shader_binary_legacy); - /* We need to calloc to prevent unintialized data because this will be used + /* We need to calloc to prevent uninitialized data because this will be used * directly for the disk cache. Uninitialized data can appear because of * padding in the struct or because legacy_binary->data can be at an offset * from the start less than sizeof(radv_shader_binary_legacy). */ diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index c4adb9b38e4..339d5af9630 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -307,7 +307,7 @@ radv_copy_thread_trace_info_regs(struct radv_device *device, struct radeon_cmdbu if (pdevice->rad_info.gfx_level >= GFX11) { /* On GFX11, SQ_THREAD_TRACE_WPTR is incremented from the "initial WPTR address" instead of 0. * To get the number of bytes (in units of 32 bytes) written by SQTT, the workaround is to - * substract SQ_THREAD_TRACE_WPTR from the "initial WPTR address" as follow: + * subtract SQ_THREAD_TRACE_WPTR from the "initial WPTR address" as follow: * * 1) get the current buffer base address for this SE * 2) shift right by 5 bits because SQ_THREAD_TRACE_WPTR is 32-byte aligned