diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index d0dea23e5be..e57509932dc 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -495,6 +495,16 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, amdgpu_device_handle dev = dev_p; drmDevicePtr devinfo; + STATIC_ASSERT(AMDGPU_HW_IP_GFX == RING_GFX); + STATIC_ASSERT(AMDGPU_HW_IP_COMPUTE == RING_COMPUTE); + STATIC_ASSERT(AMDGPU_HW_IP_DMA == RING_DMA); + STATIC_ASSERT(AMDGPU_HW_IP_UVD == RING_UVD); + STATIC_ASSERT(AMDGPU_HW_IP_VCE == RING_VCE); + STATIC_ASSERT(AMDGPU_HW_IP_UVD_ENC == RING_UVD_ENC); + STATIC_ASSERT(AMDGPU_HW_IP_VCN_DEC == RING_VCN_DEC); + STATIC_ASSERT(AMDGPU_HW_IP_VCN_ENC == RING_VCN_ENC); + STATIC_ASSERT(AMDGPU_HW_IP_VCN_JPEG == RING_VCN_JPEG); + /* Get PCI info. */ r = drmGetDevice2(fd, 0, &devinfo); if (r) { diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h index 6ab23196938..ec016c25f7c 100644 --- a/src/amd/common/amd_family.h +++ b/src/amd/common/amd_family.h @@ -156,7 +156,7 @@ enum chip_class NUM_GFX_VERSIONS, }; -enum ring_type +enum amd_ip_type { RING_GFX = 0, RING_COMPUTE, diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f0f092d6649..391a06cfea0 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -356,7 +356,7 @@ radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7; } -enum ring_type +enum amd_ip_type radv_queue_family_to_ring(struct radv_physical_device *physical_device, enum radv_queue_family f) { @@ -699,7 +699,7 @@ static void radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline) { struct radv_device *device = cmd_buffer->device; - enum ring_type ring; + enum amd_ip_type ring; uint32_t data[2]; uint64_t va; @@ -715,7 +715,7 @@ radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pip va += 16; break; default: - assert(!"invalid ring type"); + assert(!"invalid IP type"); } uint64_t pipeline_address = (uintptr_t)pipeline; diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c index c1e86867647..7e231e30e5a 100644 --- a/src/amd/vulkan/radv_debug.c +++ b/src/amd/vulkan/radv_debug.c @@ -509,7 +509,7 @@ radv_dump_vs_prolog(struct radv_pipeline *pipeline, FILE *f) } static struct radv_pipeline * -radv_get_saved_pipeline(struct radv_device *device, enum ring_type ring) +radv_get_saved_pipeline(struct radv_device *device, enum amd_ip_type ring) { uint64_t *ptr = (uint64_t *)device->trace_id_ptr; int offset = ring == RING_GFX ? 1 : 2; @@ -520,7 +520,7 @@ radv_get_saved_pipeline(struct radv_device *device, enum ring_type ring) static void radv_dump_queue_state(struct radv_queue *queue, const char *dump_dir, FILE *f) { - enum ring_type ring = radv_queue_ring(queue); + enum amd_ip_type ring = radv_queue_ring(queue); struct radv_pipeline *pipeline; fprintf(f, "RING_%s:\n", ring == RING_GFX ? "GFX" : "COMPUTE"); @@ -631,7 +631,7 @@ radv_dump_device_name(struct radv_device *device, FILE *f) static void radv_dump_umr_ring(struct radv_queue *queue, FILE *f) { - enum ring_type ring = radv_queue_ring(queue); + enum amd_ip_type ring = radv_queue_ring(queue); struct radv_device *device = queue->device; char cmd[128]; @@ -649,7 +649,7 @@ radv_dump_umr_ring(struct radv_queue *queue, FILE *f) static void radv_dump_umr_waves(struct radv_queue *queue, FILE *f) { - enum ring_type ring = radv_queue_ring(queue); + enum amd_ip_type ring = radv_queue_ring(queue); struct radv_device *device = queue->device; char cmd[128]; @@ -665,7 +665,7 @@ radv_dump_umr_waves(struct radv_queue *queue, FILE *f) } static bool -radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring) +radv_gpu_hang_occured(struct radv_queue *queue, enum amd_ip_type ring) { struct radeon_winsys *ws = queue->device->ws; @@ -679,7 +679,7 @@ void radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs) { struct radv_device *device = queue->device; - enum ring_type ring; + enum amd_ip_type ring; uint64_t addr; ring = radv_queue_ring(queue); @@ -989,7 +989,7 @@ radv_dump_sq_hw_regs(struct radv_device *device) void radv_check_trap_handler(struct radv_queue *queue) { - enum ring_type ring = radv_queue_ring(queue); + enum amd_ip_type ring = radv_queue_ring(queue); struct radv_device *device = queue->device; struct radeon_winsys *ws = device->ws; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 6334f62b826..9a500892061 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -77,7 +77,7 @@ typedef void *drmDevicePtr; #include "ac_llvm_util.h" #endif -/* The number of IBs per submit isn't infinite, it depends on the ring type +/* The number of IBs per submit isn't infinite, it depends on the IP type * (ie. some initial setup needed for a submit) and the number of IBs (4 DW). * This limit is arbitrary but should be safe for now. Ideally, we should get * this limit from the KMD. @@ -4525,7 +4525,7 @@ radv_queue_submit(struct vk_queue *vqueue, struct vk_queue_submit *submission) struct radeon_cmdbuf *initial_preamble_cs = NULL; struct radeon_cmdbuf *initial_flush_preamble_cs = NULL; struct radeon_cmdbuf *continue_preamble_cs = NULL; - enum ring_type ring = radv_queue_ring(queue); + enum amd_ip_type ring = radv_queue_ring(queue); result = radv_get_preambles(queue, submission->command_buffers, submission->command_buffer_count, diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index f5ceca1790f..9aab17de4fe 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -699,7 +699,7 @@ vk_queue_to_radv(const struct radv_physical_device *phys_dev, int queue_family_i return phys_dev->vk_queue_to_radv[queue_family_index]; } -enum ring_type radv_queue_family_to_ring(struct radv_physical_device *physical_device, +enum amd_ip_type radv_queue_family_to_ring(struct radv_physical_device *physical_device, enum radv_queue_family f); struct radv_queue { @@ -2927,7 +2927,7 @@ si_translate_blend_logic_op(VkLogicOp op) * Queue helper to get ring. * placed here as it needs queue + device structs. */ -static inline enum ring_type +static inline enum amd_ip_type radv_queue_ring(struct radv_queue *queue) { return radv_queue_family_to_ring(queue->device->physical_device, queue->qf); diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index d72b4d670d8..759e2c904bb 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -256,13 +256,13 @@ struct radeon_winsys { struct radeon_winsys_ctx **ctx); void (*ctx_destroy)(struct radeon_winsys_ctx *ctx); - bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type, int ring_index); + bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum amd_ip_type amd_ip_type, int ring_index); int (*ctx_set_pstate)(struct radeon_winsys_ctx *ctx, uint32_t pstate); enum radeon_bo_domain (*cs_domain)(const struct radeon_winsys *ws); - struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum ring_type ring_type); + struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum amd_ip_type amd_ip_type); void (*cs_destroy)(struct radeon_cmdbuf *cs); @@ -272,7 +272,7 @@ struct radeon_winsys { void (*cs_grow)(struct radeon_cmdbuf *cs, size_t min_size); - VkResult (*cs_submit)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type, int queue_index, + VkResult (*cs_submit)(struct radeon_winsys_ctx *ctx, enum amd_ip_type amd_ip_type, int queue_index, struct radeon_cmdbuf **cs_array, unsigned cs_count, struct radeon_cmdbuf *initial_preamble_cs, struct radeon_cmdbuf *continue_preamble_cs, uint32_t wait_count, diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c index 0d3a09d4401..b89f6618414 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c @@ -109,71 +109,17 @@ radv_amdgpu_cs(struct radeon_cmdbuf *base) static bool ring_can_use_ib_bos(const struct radv_amdgpu_winsys *ws, - enum ring_type ring_type) + enum amd_ip_type ip_type) { - if (ring_type == RING_UVD || - ring_type == RING_VCE || - ring_type == RING_UVD_ENC || - ring_type == RING_VCN_DEC || - ring_type == RING_VCN_ENC) + if (ip_type == RING_UVD || + ip_type == RING_VCE || + ip_type == RING_UVD_ENC || + ip_type == RING_VCN_DEC || + ip_type == RING_VCN_ENC) return false; return ws->use_ib_bos; } -static int -ring_to_hw_ip(enum ring_type ring) -{ - switch (ring) { - case RING_GFX: - return AMDGPU_HW_IP_GFX; - case RING_COMPUTE: - return AMDGPU_HW_IP_COMPUTE; - case RING_DMA: - return AMDGPU_HW_IP_DMA; - case RING_UVD: - return AMDGPU_HW_IP_UVD; - case RING_VCE: - return AMDGPU_HW_IP_VCE; - case RING_UVD_ENC: - return AMDGPU_HW_IP_UVD_ENC; - case RING_VCN_DEC: - return AMDGPU_HW_IP_VCN_DEC; - case RING_VCN_ENC: - return AMDGPU_HW_IP_VCN_ENC; - case RING_VCN_JPEG: - return AMDGPU_HW_IP_VCN_JPEG; - default: - unreachable("unsupported ring"); - } -} - -static enum ring_type -hw_ip_to_ring(int hw_ip) -{ - switch (hw_ip) { - case AMDGPU_HW_IP_GFX: - return RING_GFX; - case AMDGPU_HW_IP_COMPUTE: - return RING_COMPUTE; - case AMDGPU_HW_IP_DMA: - return RING_DMA; - case AMDGPU_HW_IP_UVD: - return RING_UVD; - case AMDGPU_HW_IP_VCE: - return RING_VCE; - case AMDGPU_HW_IP_UVD_ENC: - return RING_UVD_ENC; - case AMDGPU_HW_IP_VCN_DEC: - return RING_VCN_DEC; - case AMDGPU_HW_IP_VCN_ENC: - return RING_VCN_ENC; - case AMDGPU_HW_IP_VCN_JPEG: - return RING_VCN_JPEG; - default: - unreachable("unsupported hw ip"); - } -} - struct radv_amdgpu_cs_request { /** Specify HW IP block type to which to send the IB. */ unsigned ip_type; @@ -248,12 +194,12 @@ radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs) } static void -radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs, enum ring_type ring_type) +radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs, enum amd_ip_type ip_type) { for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i) cs->buffer_hash_table[i] = -1; - cs->hw_ip = ring_to_hw_ip(ring_type); + cs->hw_ip = ip_type; } static enum radeon_bo_domain @@ -270,19 +216,19 @@ radv_amdgpu_cs_domain(const struct radeon_winsys *_ws) } static struct radeon_cmdbuf * -radv_amdgpu_cs_create(struct radeon_winsys *ws, enum ring_type ring_type) +radv_amdgpu_cs_create(struct radeon_winsys *ws, enum amd_ip_type ip_type) { struct radv_amdgpu_cs *cs; - uint32_t ib_pad_dw_mask = MAX2(3, radv_amdgpu_winsys(ws)->info.ib_pad_dw_mask[ring_type]); + uint32_t ib_pad_dw_mask = MAX2(3, radv_amdgpu_winsys(ws)->info.ib_pad_dw_mask[ip_type]); uint32_t ib_size = align(20 * 1024 * 4, ib_pad_dw_mask + 1); cs = calloc(1, sizeof(struct radv_amdgpu_cs)); if (!cs) return NULL; cs->ws = radv_amdgpu_winsys(ws); - radv_amdgpu_init_cs(cs, ring_type); + radv_amdgpu_init_cs(cs, ip_type); - cs->use_ib = ring_can_use_ib_bos(cs->ws, ring_type); + cs->use_ib = ring_can_use_ib_bos(cs->ws, ip_type); if (cs->use_ib) { VkResult result = @@ -341,7 +287,7 @@ static uint32_t get_nop_packet(struct radv_amdgpu_cs *cs) case AMDGPU_HW_IP_VCN_DEC: return 0x81FF; default: - unreachable("Unknown ring type"); + unreachable("Unknown IP type"); } } @@ -404,8 +350,8 @@ radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size) return; } - enum ring_type ring_type = hw_ip_to_ring(cs->hw_ip); - uint32_t ib_pad_dw_mask = MAX2(3, cs->ws->info.ib_pad_dw_mask[ring_type]); + enum amd_ip_type ip_type = cs->hw_ip; + uint32_t ib_pad_dw_mask = MAX2(3, cs->ws->info.ib_pad_dw_mask[ip_type]); uint32_t nop_packet = get_nop_packet(cs); while (!cs->base.cdw || (cs->base.cdw & ib_pad_dw_mask) != ib_pad_dw_mask - 3) radeon_emit(&cs->base, nop_packet); @@ -474,10 +420,10 @@ static VkResult radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs) { struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); - enum ring_type ring_type = hw_ip_to_ring(cs->hw_ip); + enum amd_ip_type ip_type = cs->hw_ip; if (cs->use_ib) { - uint32_t ib_pad_dw_mask = MAX2(3, cs->ws->info.ib_pad_dw_mask[ring_type]); + uint32_t ib_pad_dw_mask = MAX2(3, cs->ws->info.ib_pad_dw_mask[ip_type]); uint32_t nop_packet = get_nop_packet(cs); if (hw_can_chain(cs->hw_ip)) { @@ -1102,8 +1048,8 @@ radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, int queue_id struct radv_amdgpu_winsys *aws = cs0->ws; struct radv_amdgpu_cs_request request; uint32_t pad_word = get_nop_packet(cs0); - enum ring_type ring_type = hw_ip_to_ring(cs0->hw_ip); - uint32_t ib_pad_dw_mask = cs0->ws->info.ib_pad_dw_mask[ring_type]; + enum amd_ip_type ip_type = cs0->hw_ip; + uint32_t ib_pad_dw_mask = cs0->ws->info.ib_pad_dw_mask[ip_type]; bool emit_signal_sem = sem_info->cs_emit_signal; VkResult result; @@ -1278,10 +1224,10 @@ radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, int queue_id } static VkResult -radv_amdgpu_cs_submit_zero(struct radv_amdgpu_ctx *ctx, enum ring_type ring_type, int queue_idx, +radv_amdgpu_cs_submit_zero(struct radv_amdgpu_ctx *ctx, enum amd_ip_type ip_type, int queue_idx, struct radv_winsys_sem_info *sem_info) { - unsigned hw_ip = ring_to_hw_ip(ring_type); + unsigned hw_ip = ip_type; unsigned queue_syncobj = radv_amdgpu_ctx_queue_syncobj(ctx, hw_ip, queue_idx); int ret; @@ -1368,7 +1314,7 @@ radv_amdgpu_cs_submit_zero(struct radv_amdgpu_ctx *ctx, enum ring_type ring_type } static VkResult -radv_amdgpu_winsys_cs_submit_internal(struct radeon_winsys_ctx *_ctx, enum ring_type ring_type, +radv_amdgpu_winsys_cs_submit_internal(struct radeon_winsys_ctx *_ctx, enum amd_ip_type ip_type, int queue_idx, struct radeon_cmdbuf **cs_array, unsigned cs_count, struct radeon_cmdbuf *initial_preamble_cs, struct radeon_cmdbuf *continue_preamble_cs, @@ -1379,8 +1325,8 @@ radv_amdgpu_winsys_cs_submit_internal(struct radeon_winsys_ctx *_ctx, enum ring_ assert(sem_info); if (!cs_count) { - result = radv_amdgpu_cs_submit_zero(ctx, ring_type, queue_idx, sem_info); - } else if (!ring_can_use_ib_bos(ctx->ws, ring_type)) { + result = radv_amdgpu_cs_submit_zero(ctx, ip_type, queue_idx, sem_info); + } else if (!ring_can_use_ib_bos(ctx->ws, ip_type)) { result = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, cs_array, cs_count, initial_preamble_cs, continue_preamble_cs); } else if (can_patch) { @@ -1395,7 +1341,7 @@ radv_amdgpu_winsys_cs_submit_internal(struct radeon_winsys_ctx *_ctx, enum ring_ } static VkResult -radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx, enum ring_type ring_type, +radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx, enum amd_ip_type ip_type, int queue_idx, struct radeon_cmdbuf **cs_array, unsigned cs_count, struct radeon_cmdbuf *initial_preamble_cs, struct radeon_cmdbuf *continue_preamble_cs, uint32_t wait_count, @@ -1455,7 +1401,7 @@ radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx, enum ring_type ring sem_info.signal.syncobj_count = signal_idx - sem_info.signal.timeline_syncobj_count; sem_info.cs_emit_signal = true; - result = radv_amdgpu_winsys_cs_submit_internal(_ctx, ring_type, queue_idx, cs_array, cs_count, + result = radv_amdgpu_winsys_cs_submit_internal(_ctx, ip_type, queue_idx, cs_array, cs_count, initial_preamble_cs, continue_preamble_cs, &sem_info, can_patch); @@ -1604,10 +1550,9 @@ radv_amdgpu_ctx_queue_syncobj(struct radv_amdgpu_ctx *ctx, unsigned ip, unsigned } static bool -radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx, enum ring_type ring_type, int ring_index) +radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx, enum amd_ip_type ip_type, int ring_index) { struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx; - int ip_type = ring_to_hw_ip(ring_type); if (ctx->last_submission[ip_type][ring_index].fence.fence) { uint32_t expired; diff --git a/src/amd/vulkan/winsys/null/radv_null_cs.c b/src/amd/vulkan/winsys/null/radv_null_cs.c index 4f66a980faf..fb17137a9d7 100644 --- a/src/amd/vulkan/winsys/null/radv_null_cs.c +++ b/src/amd/vulkan/winsys/null/radv_null_cs.c @@ -66,7 +66,7 @@ radv_null_cs_domain(const struct radeon_winsys *_ws) } static struct radeon_cmdbuf * -radv_null_cs_create(struct radeon_winsys *ws, enum ring_type ring_type) +radv_null_cs_create(struct radeon_winsys *ws, enum amd_ip_type ip_type) { struct radv_null_cs *cs = calloc(1, sizeof(struct radv_null_cs)); if (!cs) diff --git a/src/gallium/drivers/r600/r600_pipe_common.h b/src/gallium/drivers/r600/r600_pipe_common.h index 341511d5574..0ff827ef4c2 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.h +++ b/src/gallium/drivers/r600/r600_pipe_common.h @@ -615,7 +615,7 @@ struct r600_common_context { void (*check_vm_faults)(struct r600_common_context *ctx, struct radeon_saved_cs *saved, - enum ring_type ring); + enum amd_ip_type ring); }; /* r600_buffer_common.c */ diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c index 923d3556b8a..0dd59057985 100644 --- a/src/gallium/drivers/radeonsi/si_debug.c +++ b/src/gallium/drivers/radeonsi/si_debug.c @@ -1076,7 +1076,7 @@ void si_log_compute_state(struct si_context *sctx, struct u_log_context *log) si_dump_compute_descriptors(sctx, log); } -void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved, enum ring_type ring) +void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved, enum amd_ip_type ring) { struct pipe_screen *screen = sctx->b.screen; FILE *f; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 4eae5b63efc..ebbee0b8aac 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1465,7 +1465,7 @@ void si_log_draw_state(struct si_context *sctx, struct u_log_context *log); void si_log_compute_state(struct si_context *sctx, struct u_log_context *log); void si_init_debug_functions(struct si_context *sctx); void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved, - enum ring_type ring); + enum amd_ip_type ring); bool si_replace_shader(unsigned num, struct si_shader_binary *binary); void si_print_current_ib(struct si_context *sctx, FILE *f); diff --git a/src/gallium/include/winsys/radeon_winsys.h b/src/gallium/include/winsys/radeon_winsys.h index 560cda9d8e7..06652e35e63 100644 --- a/src/gallium/include/winsys/radeon_winsys.h +++ b/src/gallium/include/winsys/radeon_winsys.h @@ -479,14 +479,14 @@ struct radeon_winsys { * * \param cs The returned structure that is initialized by cs_create. * \param ctx The submission context - * \param ring_type The ring type (GFX, DMA, UVD) + * \param ip_type The IP type (GFX, DMA, UVD) * \param flush Flush callback function associated with the command stream. * \param user User pointer that will be passed to the flush callback. * * \return true on success */ bool (*cs_create)(struct radeon_cmdbuf *cs, - struct radeon_winsys_ctx *ctx, enum ring_type ring_type, + struct radeon_winsys_ctx *ctx, enum amd_ip_type amd_ip_type, void (*flush)(void *ctx, unsigned flags, struct pipe_fence_handle **fence), void *flush_ctx, bool stop_exec_on_failure); diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index fc2340a0680..4ba7e984d66 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -717,9 +717,9 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, enum radeon_bo_domain domain; unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING; - if (cs->ring_type == RING_GFX || - cs->ring_type == RING_COMPUTE || - cs->ring_type == RING_DMA) { + if (cs->ip_type == RING_GFX || + cs->ip_type == RING_COMPUTE || + cs->ip_type == RING_DMA) { domain = ws->info.smart_access_memory ? RADEON_DOMAIN_VRAM : RADEON_DOMAIN_GTT; flags |= RADEON_FLAG_32BIT | RADEON_FLAG_GTT_WC; } else { @@ -829,9 +829,9 @@ static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct radeon_cmdbuf *r static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs, - enum ring_type ring_type) + enum amd_ip_type ip_type) { - switch (ring_type) { + switch (ip_type) { case RING_DMA: cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_DMA; break; @@ -862,7 +862,7 @@ static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws, case RING_COMPUTE: case RING_GFX: - cs->ib[IB_MAIN].ip_type = ring_type == RING_GFX ? AMDGPU_HW_IP_GFX : + cs->ib[IB_MAIN].ip_type = ip_type == RING_GFX ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_COMPUTE; /* The kernel shouldn't invalidate L2 and vL1. The proper place for cache @@ -931,7 +931,7 @@ static void amdgpu_destroy_cs_context(struct amdgpu_winsys *ws, struct amdgpu_cs static bool amdgpu_cs_create(struct radeon_cmdbuf *rcs, struct radeon_winsys_ctx *rwctx, - enum ring_type ring_type, + enum amd_ip_type ip_type, void (*flush)(void *ctx, unsigned flags, struct pipe_fence_handle **fence), void *flush_ctx, @@ -951,25 +951,25 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs, cs->ctx = ctx; cs->flush_cs = flush; cs->flush_data = flush_ctx; - cs->ring_type = ring_type; + cs->ip_type = ip_type; cs->stop_exec_on_failure = stop_exec_on_failure; cs->noop = ctx->ws->noop_cs; cs->has_chaining = ctx->ws->info.chip_class >= GFX7 && - (ring_type == RING_GFX || ring_type == RING_COMPUTE); + (ip_type == RING_GFX || ip_type == RING_COMPUTE); struct amdgpu_cs_fence_info fence_info; fence_info.handle = cs->ctx->user_fence_bo; - fence_info.offset = cs->ring_type * 4; + fence_info.offset = cs->ip_type * 4; amdgpu_cs_chunk_fence_info_to_data(&fence_info, (void*)&cs->fence_chunk); cs->main.ib_type = IB_MAIN; - if (!amdgpu_init_cs_context(ctx->ws, &cs->csc1, ring_type)) { + if (!amdgpu_init_cs_context(ctx->ws, &cs->csc1, ip_type)) { FREE(cs); return false; } - if (!amdgpu_init_cs_context(ctx->ws, &cs->csc2, ring_type)) { + if (!amdgpu_init_cs_context(ctx->ws, &cs->csc2, ip_type)) { amdgpu_destroy_cs_context(ctx->ws, &cs->csc1); FREE(cs); return false; @@ -1034,7 +1034,7 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i memcpy(map, preamble_ib, preamble_num_dw * 4); /* Pad the IB. */ - uint32_t ib_pad_dw_mask = ws->info.ib_pad_dw_mask[cs->ring_type]; + uint32_t ib_pad_dw_mask = ws->info.ib_pad_dw_mask[cs->ip_type]; while (preamble_num_dw & ib_pad_dw_mask) map[preamble_num_dw++] = PKT3_NOP_PAD; amdgpu_bo_unmap(&ws->dummy_ws.base, preamble_bo); @@ -1112,7 +1112,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) rcs->current.max_dw += cs_epilog_dw; /* Pad with NOPs but leave 4 dwords for INDIRECT_BUFFER. */ - uint32_t ib_pad_dw_mask = cs->ws->info.ib_pad_dw_mask[cs->ring_type]; + uint32_t ib_pad_dw_mask = cs->ws->info.ib_pad_dw_mask[cs->ip_type]; while ((rcs->current.cdw & ib_pad_dw_mask) != ib_pad_dw_mask - 3) radeon_emit(rcs, PKT3_NOP_PAD); @@ -1194,8 +1194,8 @@ static bool is_noop_fence_dependency(struct amdgpu_cs *acs, * We always want no dependency between back-to-back gfx IBs, because * we need the parallelism between IBs for good performance. */ - if ((acs->ring_type == RING_GFX || - acs->ws->info.num_rings[acs->ring_type] == 1) && + if ((acs->ip_type == RING_GFX || + acs->ws->info.num_rings[acs->ip_type] == 1) && !amdgpu_fence_is_syncobj(fence) && fence->ctx == acs->ctx && fence->fence.ip_type == cs->ib[IB_MAIN].ip_type) @@ -1455,7 +1455,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) } } - if (acs->ring_type == RING_GFX) + if (acs->ip_type == RING_GFX) ws->gfx_bo_list_counter += cs->num_real_buffers; bool noop = false; @@ -1571,7 +1571,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) /* Apply RADEON_NOOP. */ if (acs->noop) { - if (acs->ring_type == RING_GFX) { + if (acs->ip_type == RING_GFX) { /* Reduce the IB size and fill it with NOP to make it like an empty IB. */ unsigned noop_size = MIN2(cs->ib[IB_MAIN].ib_bytes, ws->info.ib_alignment); @@ -1610,7 +1610,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) * QWORD[3]: preempted then reset **/ if (has_user_fence) - user_fence = acs->ctx->user_fence_cpu_address_base + acs->ring_type * 4; + user_fence = acs->ctx->user_fence_cpu_address_base + acs->ip_type * 4; amdgpu_fence_submitted(cs->fence, seq_no, user_fence); } @@ -1653,12 +1653,12 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, struct amdgpu_cs *cs = amdgpu_cs(rcs); struct amdgpu_winsys *ws = cs->ws; int error_code = 0; - uint32_t ib_pad_dw_mask = ws->info.ib_pad_dw_mask[cs->ring_type]; + uint32_t ib_pad_dw_mask = ws->info.ib_pad_dw_mask[cs->ip_type]; rcs->current.max_dw += amdgpu_cs_epilog_dws(cs); /* Pad the IB according to the mask. */ - switch (cs->ring_type) { + switch (cs->ip_type) { case RING_DMA: if (ws->info.chip_class <= GFX6) { while (rcs->current.cdw & ib_pad_dw_mask) @@ -1677,7 +1677,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, while (rcs->current.cdw & ib_pad_dw_mask) radeon_emit(rcs, PKT3_NOP_PAD); } - if (cs->ring_type == RING_GFX) + if (cs->ip_type == RING_GFX) ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4; break; case RING_UVD: @@ -1768,9 +1768,9 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, rcs->used_gart_kb = 0; rcs->used_vram_kb = 0; - if (cs->ring_type == RING_GFX) + if (cs->ip_type == RING_GFX) ws->num_gfx_IBs++; - else if (cs->ring_type == RING_DMA) + else if (cs->ip_type == RING_DMA) ws->num_sdma_IBs++; return error_code; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h index 794d13bd00b..5898871a0a0 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h @@ -131,7 +131,7 @@ struct amdgpu_cs { struct amdgpu_ib main; /* must be first because this is inherited */ struct amdgpu_winsys *ws; struct amdgpu_ctx *ctx; - enum ring_type ring_type; + enum amd_ip_type ip_type; struct drm_amdgpu_cs_chunk_fence fence_chunk; /* We flip between these two CS. While one is being consumed diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c index f220b98969d..0e1a6e7e64e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c @@ -172,7 +172,7 @@ static void radeon_destroy_cs_context(struct radeon_cs_context *csc) static bool radeon_drm_cs_create(struct radeon_cmdbuf *rcs, struct radeon_winsys_ctx *ctx, - enum ring_type ring_type, + enum amd_ip_type ip_type, void (*flush)(void *ctx, unsigned flags, struct pipe_fence_handle **fence), void *flush_ctx, @@ -204,7 +204,7 @@ radeon_drm_cs_create(struct radeon_cmdbuf *rcs, /* Set the first command buffer as current. */ cs->csc = &cs->csc1; cs->cst = &cs->csc2; - cs->ring_type = ring_type; + cs->ip_type = ip_type; memset(rcs, 0, sizeof(*rcs)); rcs->current.buf = cs->csc->buf; @@ -274,7 +274,7 @@ static unsigned radeon_lookup_or_add_real_buffer(struct radeon_drm_cs *cs, * This doesn't have to be done if virtual memory is enabled, * because there is no offset patching with virtual memory. */ - if (cs->ring_type != RING_DMA || cs->ws->info.r600_has_virtual_memory) { + if (cs->ip_type != RING_DMA || cs->ws->info.r600_has_virtual_memory) { return i; } } @@ -578,7 +578,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs, struct radeon_drm_cs *cs = radeon_drm_cs(rcs); struct radeon_cs_context *tmp; - switch (cs->ring_type) { + switch (cs->ip_type) { case RING_DMA: /* pad DMA ring to 8 DWs */ if (cs->ws->info.chip_class <= GFX6) { @@ -662,7 +662,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs, p_atomic_inc(&cs->cst->relocs_bo[i].bo->num_active_ioctls); } - switch (cs->ring_type) { + switch (cs->ip_type) { case RING_DMA: cs->cst->flags[0] = 0; cs->cst->flags[1] = RADEON_CS_RING_DMA; @@ -699,7 +699,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs, cs->cst->flags[0] |= RADEON_CS_END_OF_FRAME; cs->cst->cs.num_chunks = 3; } - if (cs->ring_type == RING_COMPUTE) { + if (cs->ip_type == RING_COMPUTE) { cs->cst->flags[1] = RADEON_CS_RING_COMPUTE; cs->cst->cs.num_chunks = 3; } @@ -724,9 +724,9 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs, rcs->used_vram_kb = 0; rcs->used_gart_kb = 0; - if (cs->ring_type == RING_GFX) + if (cs->ip_type == RING_GFX) cs->ws->num_gfx_IBs++; - else if (cs->ring_type == RING_DMA) + else if (cs->ip_type == RING_DMA) cs->ws->num_sdma_IBs++; return 0; } diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h index bda22bc347c..bc2daf665ae 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h @@ -70,7 +70,7 @@ struct radeon_cs_context { }; struct radeon_drm_cs { - enum ring_type ring_type; + enum amd_ip_type ip_type; /* We flip between these two CS. While one is being consumed * by the kernel in another thread, the other one is being filled