anv/state: Replace a bunch of ANV_GEN with GEN_GEN
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@@ -44,7 +44,7 @@ genX(init_device_state)(struct anv_device *device)
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batch.end = (void *) cmds + sizeof(cmds);
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anv_batch_emit(&batch, GENX(PIPELINE_SELECT),
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#if ANV_GEN >= 9
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#if GEN_GEN >= 9
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.MaskBits = 3,
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#endif
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.PipelineSelection = _3D);
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@@ -93,7 +93,7 @@ genX(init_device_state)(struct anv_device *device)
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._8xSample6YOffset = 0.9375,
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._8xSample7XOffset = 0.9375,
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._8xSample7YOffset = 0.0625,
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#if ANV_GEN >= 9
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#if GEN_GEN >= 9
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._16xSample0XOffset = 0.5625,
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._16xSample0YOffset = 0.5625,
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._16xSample1XOffset = 0.4375,
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@@ -194,7 +194,7 @@ static const uint8_t anv_valign[] = {
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static void
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get_halign_valign(const struct isl_surf *surf, uint32_t *halign, uint32_t *valign)
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{
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#if ANV_GENx10 >= 90
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#if GEN_GEN >= 9
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if (isl_tiling_is_std_y(surf->tiling) ||
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surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
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/* The hardware ignores the alignment values. Anyway, the surface's
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@@ -239,7 +239,7 @@ get_qpitch(const struct isl_surf *surf)
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default:
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unreachable(!"bad isl_surf_dim");
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case ISL_SURF_DIM_1D:
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#if ANV_GENx10 >= 90
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#if GEN_GEN >= 9
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/* QPitch is usually expressed as rows of surface elements (where
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* a surface element is an compression block or a single surface
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* sample). Skylake 1D is an outlier.
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@@ -256,7 +256,7 @@ get_qpitch(const struct isl_surf *surf)
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#endif
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case ISL_SURF_DIM_2D:
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case ISL_SURF_DIM_3D:
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#if ANV_GEN >= 9
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#if GEN_GEN >= 9
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return isl_surf_get_array_pitch_el_rows(surf);
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#else
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/* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
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@@ -452,7 +452,7 @@ VkResult genX(CreateSampler)(
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.SamplerDisable = false,
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.TextureBorderColorMode = DX10OGL,
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.LODPreClampMode = CLAMP_MODE_OGL,
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#if ANV_GEN == 8
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#if GEN_GEN == 8
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.BaseMipLevel = 0.0,
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#endif
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.MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode],
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