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anv: add missing transition handling bits

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New access flags & pipeline stages got added for transform feedback
and we missed handling them.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9045>
This commit is contained in:
Lionel Landwerlin
2020-11-11 11:36:33 +02:00
committed by Marge Bot
parent 97f0a4494b
commit ad9d95eee4
2 changed files with 17 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/intel/vulkan/anv_private.h
View File

@@ -2596,6 +2596,14 @@ anv_pipe_flush_bits_for_access_flags(struct anv_device *device,
pipe_bits |= ANV_PIPE_FLUSH_BITS; pipe_bits |= ANV_PIPE_FLUSH_BITS;
pipe_bits |= ANV_PIPE_INVALIDATE_BITS; pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
break; break;
case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
/* We're transitioning a buffer written either from VS stage or from
* the command streamer (see CmdEndTransformFeedbackEXT), we just
* need to stall the CS.
*/
pipe_bits |= ANV_PIPE_CS_STALL_BIT;
break;
default: default:
break; /* Nothing to do */ break; /* Nothing to do */
} }
@@ -2675,11 +2683,12 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
pipe_bits |= ANV_PIPE_FLUSH_BITS; pipe_bits |= ANV_PIPE_FLUSH_BITS;
break; break;
case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT: case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT:
/* Transitioning a buffer for conditional rendering. We'll load the case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT:
* content of this buffer into HW registers using the command /* Transitioning a buffer for conditional rendering or transform
* streamer, so we need to stall the command streamer to make sure * feedback. We'll load the content of this buffer into HW registers
* any in-flight flush operations have completed. Needs tile cache * using the command streamer, so we need to stall the command
* and data cache flush because command stream isn't L3 coherent yet. * streamer , so we need to stall the command streamer to make sure
* any in-flight flush operations have completed.
*/ */
pipe_bits |= ANV_PIPE_CS_STALL_BIT; pipe_bits |= ANV_PIPE_CS_STALL_BIT;
pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT; pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;

3
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -6879,7 +6879,8 @@ void genX(CmdEndConditionalRenderingEXT)(
VK_PIPELINE_STAGE_TRANSFER_BIT | \ VK_PIPELINE_STAGE_TRANSFER_BIT | \
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \ VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \ VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
VK_PIPELINE_STAGE_ALL_COMMANDS_BIT) VK_PIPELINE_STAGE_ALL_COMMANDS_BIT | \
VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)
void genX(CmdSetEvent)( void genX(CmdSetEvent)(
VkCommandBuffer commandBuffer, VkCommandBuffer commandBuffer,