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gallium: remove TGSI_OPCODE_CLAMP

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Not used and not widely supported. Use MIN+MAX instead.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-02-16 18:01:53 +01:00
parent 675ef9c0c7
commit ad019bf5c6
14 changed files with 5 additions and 86 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
View File

@@ -110,21 +110,6 @@ arr_emit(
bld_base->uint_bld.vec_type, "");
}
/* TGSI_OPCODE_CLAMP */
static void
clamp_emit(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMValueRef tmp;
tmp = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
emit_data->args[0],
emit_data->args[1]);
emit_data->output[emit_data->chan] = lp_build_emit_llvm_binary(bld_base,
TGSI_OPCODE_MIN, tmp, emit_data->args[2]);
}
/* DP* Helper */
static void
@@ -1330,7 +1315,6 @@ lp_set_default_actions(struct lp_build_tgsi_context * bld_base)
bld_base->op_actions[TGSI_OPCODE_ADD].emit = add_emit;
bld_base->op_actions[TGSI_OPCODE_ARR].emit = arr_emit;
bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = clamp_emit;
bld_base->op_actions[TGSI_OPCODE_END].emit = end_emit;
bld_base->op_actions[TGSI_OPCODE_FRC].emit = frc_emit;
bld_base->op_actions[TGSI_OPCODE_LRP].emit = lrp_emit;

8
src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
View File

@@ -609,14 +609,6 @@ lp_emit_instruction_aos(
dst0 = lp_build_sub(&bld->bld_base.base, src0, tmp0);
break;
case TGSI_OPCODE_CLAMP:
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
src1 = lp_build_emit_fetch(&bld->bld_base, inst, 1, LP_CHAN_ALL);
src2 = lp_build_emit_fetch(&bld->bld_base, inst, 2, LP_CHAN_ALL);
tmp0 = lp_build_max(&bld->bld_base.base, src0, src1);
dst0 = lp_build_min(&bld->bld_base.base, tmp0, src2);
break;
case TGSI_OPCODE_FLR:
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
dst0 = lp_build_floor(&bld->bld_base.base, src0);

11
src/gallium/auxiliary/nir/tgsi_to_nir.c
View File

@@ -985,12 +985,6 @@ ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
}
static void
ttn_clamp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
{
ttn_move_dest(b, dest, nir_fmin(b, nir_fmax(b, src[0], src[1]), src[2]));
}
static void
ttn_xpd(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
{
@@ -1539,7 +1533,6 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_SQRT] = nir_op_fsqrt,
[TGSI_OPCODE_DP2A] = 0,
[TGSI_OPCODE_FRC] = nir_op_ffract,
[TGSI_OPCODE_CLAMP] = 0,
[TGSI_OPCODE_FLR] = nir_op_ffloor,
[TGSI_OPCODE_ROUND] = nir_op_fround_even,
[TGSI_OPCODE_EX2] = nir_op_fexp2,
@@ -1765,10 +1758,6 @@ ttn_emit_instruction(struct ttn_compile *c)
ttn_lit(b, op_trans[tgsi_op], dest, src);
break;
case TGSI_OPCODE_CLAMP:
ttn_clamp(b, op_trans[tgsi_op], dest, src);
break;
case TGSI_OPCODE_XPD:
ttn_xpd(b, op_trans[tgsi_op], dest, src);
break;

16
src/gallium/auxiliary/tgsi/tgsi_exec.c
View File

@@ -126,18 +126,6 @@ micro_ceil(union tgsi_exec_channel *dst,
dst->f[3] = ceilf(src->f[3]);
}
static void
micro_clamp(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src0,
const union tgsi_exec_channel *src1,
const union tgsi_exec_channel *src2)
{
dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
}
static void
micro_cmp(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src0,
@@ -5234,10 +5222,6 @@ exec_instruction(
exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_CLAMP:
exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_FLR:
exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;

2
src/gallium/auxiliary/tgsi/tgsi_info.c
View File

@@ -62,7 +62,7 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, 0, COMP, "F2U64", TGSI_OPCODE_F2U64 },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "F2I64", TGSI_OPCODE_F2I64 },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "FRC", TGSI_OPCODE_FRC },
{ 1, 3, 0, 0, 0, 0, 0, COMP, "CLAMP", TGSI_OPCODE_CLAMP },
{ 1, 3, 0, 0, 0, 0, 0, COMP, "", 25 }, /* removed */
{ 1, 1, 0, 0, 0, 0, 0, COMP, "FLR", TGSI_OPCODE_FLR },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "ROUND", TGSI_OPCODE_ROUND },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "EX2", TGSI_OPCODE_EX2 },

1
src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
View File

@@ -77,7 +77,6 @@ OP13(LRP)
OP11(SQRT)
OP13(DP2A)
OP11(FRC)
OP13(CLAMP)
OP11(FLR)
OP11(ROUND)
OP11(EX2)

1
src/gallium/auxiliary/tgsi/tgsi_util.c
View File

@@ -196,7 +196,6 @@ tgsi_util_get_inst_usage_mask(const struct tgsi_full_instruction *inst,
case TGSI_OPCODE_FMA:
case TGSI_OPCODE_FRC:
case TGSI_OPCODE_CEIL:
case TGSI_OPCODE_CLAMP:
case TGSI_OPCODE_FLR:
case TGSI_OPCODE_ROUND:
case TGSI_OPCODE_POW:

13
src/gallium/docs/source/tgsi.rst
View File

@@ -300,19 +300,6 @@ Perform a * b + c with no intermediate rounding step.
dst.w = src.w - \lfloor src.w\rfloor
.. opcode:: CLAMP - Clamp
.. math::
dst.x = clamp(src0.x, src1.x, src2.x)
dst.y = clamp(src0.y, src1.y, src2.y)
dst.z = clamp(src0.z, src1.z, src2.z)
dst.w = clamp(src0.w, src1.w, src2.w)
.. opcode:: FLR - Floor
.. math::

10
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
View File

@@ -3366,16 +3366,6 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
->rnd = ROUND_NI;
break;
case TGSI_OPCODE_CLAMP:
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
src0 = fetchSrc(0, c);
src1 = fetchSrc(1, c);
src2 = fetchSrc(2, c);
val0 = getScratch();
mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
}
break;
case TGSI_OPCODE_SLT:
case TGSI_OPCODE_SGE:
case TGSI_OPCODE_SEQ:

1
src/gallium/drivers/r300/r300_tgsi_to_rc.c
View File

@@ -53,7 +53,6 @@ static unsigned translate_opcode(unsigned opcode)
case TGSI_OPCODE_LRP: return RC_OPCODE_LRP;
/* case TGSI_OPCODE_DP2A: return RC_OPCODE_DP2A; */
case TGSI_OPCODE_FRC: return RC_OPCODE_FRC;
case TGSI_OPCODE_CLAMP: return RC_OPCODE_CLAMP;
case TGSI_OPCODE_FLR: return RC_OPCODE_FLR;
case TGSI_OPCODE_ROUND: return RC_OPCODE_ROUND;
case TGSI_OPCODE_EX2: return RC_OPCODE_EX2;

6
src/gallium/drivers/r600/r600_shader.c
View File

@@ -9097,7 +9097,7 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[]
[22] = { ALU_OP0_NOP, tgsi_unsupported},
[23] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
[TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
[25] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
[TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
[TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
@@ -9295,7 +9295,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
[22] = { ALU_OP0_NOP, tgsi_unsupported},
[23] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
[TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
[25] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
[TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
[TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
@@ -9518,7 +9518,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
[22] = { ALU_OP0_NOP, tgsi_unsupported},
[23] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
[TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
[25] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
[TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
[TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},

3
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
View File

@@ -733,9 +733,6 @@ void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base)
HAVE_LLVM >= 0x0308 ? "llvm.bitreverse.i32" : "llvm.AMDGPU.brev";
bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.ceil.f32";
bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name =
HAVE_LLVM >= 0x0308 ? "llvm.AMDGPU.clamp." : "llvm.AMDIL.clamp.";
bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cmp;
bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";

1
src/gallium/drivers/svga/svga_tgsi_insn.c
View File

@@ -3000,7 +3000,6 @@ svga_emit_instruction(struct svga_shader_emitter *emit,
/* These aren't actually used by any of the frontends we care
* about:
*/
case TGSI_OPCODE_CLAMP:
case TGSI_OPCODE_AND:
case TGSI_OPCODE_OR:
case TGSI_OPCODE_I2F:

2
src/gallium/include/pipe/p_shader_tokens.h
View File

@@ -354,7 +354,7 @@ struct tgsi_property_data {
#define TGSI_OPCODE_F2U64 22
#define TGSI_OPCODE_F2I64 23
#define TGSI_OPCODE_FRC 24
#define TGSI_OPCODE_CLAMP 25
/* gap */
#define TGSI_OPCODE_FLR 26
#define TGSI_OPCODE_ROUND 27
#define TGSI_OPCODE_EX2 28