radeon: Move r600_need_dma_space to common code

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Niels Ole Salscheider
2014-03-17 18:48:05 +01:00
committed by Marek Olšák
parent f4b3430a36
commit acf55e7325
7 changed files with 15 additions and 15 deletions

View File

@@ -62,7 +62,7 @@ void evergreen_dma_copy(struct r600_context *rctx,
}
ncopy = (size / 0x000fffff) + !!(size % 0x000fffff);
r600_need_dma_space(rctx, ncopy * 5);
r600_need_dma_space(&rctx->b, ncopy * 5);
for (i = 0; i < ncopy; i++) {
csize = size < 0x000fffff ? size : 0x000fffff;
/* emit reloc before writting cs so that cs is always in consistent state */

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@@ -3295,7 +3295,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
size = (copy_height * pitch) >> 2;
ncopy = (size / 0x000fffff) + !!(size % 0x000fffff);
r600_need_dma_space(rctx, ncopy * 9);
r600_need_dma_space(&rctx->b, ncopy * 9);
for (i = 0; i < ncopy; i++) {
cheight = copy_height;

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@@ -440,16 +440,6 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
R600_CONTEXT_INV_TEX_CACHE;
}
void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
{
/* The number of dwords we already used in the DMA so far. */
num_dw += ctx->b.rings.dma.cs->cdw;
/* Flush if there's not enough space. */
if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
ctx->b.rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
}
}
void r600_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
@@ -475,7 +465,7 @@ void r600_dma_copy(struct r600_context *rctx,
shift = 2;
ncopy = (size / 0xffff) + !!(size % 0xffff);
r600_need_dma_space(rctx, ncopy * 5);
r600_need_dma_space(&rctx->b, ncopy * 5);
for (i = 0; i < ncopy; i++) {
csize = size < 0xffff ? size : 0xffff;
/* emit reloc before writting cs so that cs is always in consistent state */

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@@ -586,7 +586,6 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags);
void r600_begin_new_cs(struct r600_context *ctx);
void r600_flush_emit(struct r600_context *ctx);
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
void r600_cp_dma_copy_buffer(struct r600_context *rctx,
struct pipe_resource *dst, uint64_t dst_offset,
struct pipe_resource *src, uint64_t src_offset,

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@@ -2856,7 +2856,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
*/
cheight = ((0x0000ffff << 2) / pitch) & 0xfffffff8;
ncopy = (copy_height / cheight) + !!(copy_height % cheight);
r600_need_dma_space(rctx, ncopy * 7);
r600_need_dma_space(&rctx->b, ncopy * 7);
for (i = 0; i < ncopy; i++) {
cheight = cheight > copy_height ? copy_height : cheight;

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@@ -39,6 +39,16 @@
* pipe_context
*/
void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
{
/* The number of dwords we already used in the DMA so far. */
num_dw += ctx->rings.dma.cs->cdw;
/* Flush if there's not enough space. */
if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
}
}
static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
{
}

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@@ -409,6 +409,7 @@ void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_re
struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
const struct pipe_resource *templ);
const char *r600_get_llvm_processor_name(enum radeon_family family);
void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
/* r600_query.c */
void r600_query_init(struct r600_common_context *rctx);