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tu/a7xx: Correctly set A7XX_HLSQ_UNKNOWN_A9AE.SYSVAL_REGS_COUNT

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Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
This commit is contained in:
Danylo Piliaiev
2023-12-14 13:56:05 +01:00
committed by Marge Bot
parent bc6b847017
commit ac75edb8c4
3 changed files with 33 additions and 4 deletions
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7
src/freedreno/registers/adreno/a6xx.xml
View File

@@ -4298,9 +4298,12 @@ to upconvert to 32b float internally?
<!-- Used in VK_KHR_fragment_shading_rate -->
<reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-"/>
<reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="cmd">
<bitfield name="UNK0" low="0" high="7" type="uint"/>
<reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">
<bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>
<!-- UNK8 is set on a730/a740 -->
<bitfield name="UNK8" pos="8" type="boolean"/>
<!-- UNK9 is set on a750 -->
<bitfield name="UNK9" pos="9" type="boolean"/>
</reg32>
<reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>

1
src/freedreno/vulkan/tu_clear_blit.cc
View File

@@ -862,7 +862,6 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
tu6_emit_vpc<CHIP>(cs, vs, NULL, NULL, NULL, fs);
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs, A7XX_HLSQ_UNKNOWN_A9AE(.unk0 = 0x2, .unk8 = 1));
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.consts_load_disable = false));

29
src/freedreno/vulkan/tu_shader.cc
View File

@@ -21,6 +21,8 @@
#include "tu_pipeline.h"
#include "tu_lrz.h"
#include <initializer_list>
nir_shader *
tu_spirv_to_nir(struct tu_device *dev,
void *mem_ctx,
@@ -1525,6 +1527,32 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
.zwcoordregid = zwcoord_regid),
HLSQ_CONTROL_5_REG(CHIP, .dword = 0xfcfc), );
if (CHIP >= A7XX) {
uint32_t sysval_regs = 0;
for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++) {
if (VALIDREG(ij_regid[i])) {
if (i == IJ_PERSP_CENTER_RHW)
sysval_regs += 1;
else
sysval_regs += 2;
}
}
for (uint32_t sysval : { face_regid, samp_id_regid, smask_in_regid }) {
if (VALIDREG(sysval))
sysval_regs += 1;
}
for (uint32_t sysval : { coord_regid, zwcoord_regid }) {
if (VALIDREG(sysval))
sysval_regs += 2;
}
tu_cs_emit_regs(cs, A7XX_HLSQ_UNKNOWN_A9AE(.sysval_regs_count = sysval_regs,
.unk8 = 1,
.unk9 = 1));
}
enum a6xx_threadsize thrsz = fs->info.double_threadsize ? THREAD128 : THREAD64;
tu_cs_emit_regs(cs, HLSQ_FS_CNTL_0(CHIP, .threadsize = thrsz, .varyings = enable_varyings));
@@ -1846,7 +1874,6 @@ tu6_emit_fs(struct tu_cs *cs,
tu_cs_emit_regs(cs, A6XX_PC_PS_CNTL(.primitiveiden = fs && fs->reads_primid));
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs, A7XX_HLSQ_UNKNOWN_A9AE(.unk0 = 0x2, .unk8 = 1));
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.consts_load_disable = false));
}