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intel: Rename gen field in gen_device_info struct to ver

Browse Source 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)gen" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)gen/info\1\2ver/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
This commit is contained in:
Anuj Phogat
2021-03-29 14:41:58 -07:00
committed by Marge Bot
parent 99331f6deb
commit abe9a71a09
166 changed files with 1904 additions and 1904 deletions
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28
src/intel/compiler/brw_compiler.c
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@@ -106,15 +106,15 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
compiler->use_tcs_8_patch =
devinfo->gen >= 12 ||
(devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH));
devinfo->ver >= 12 ||
(devinfo->ver >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH));
/* Default to the sampler since that's what we've done since forever */
compiler->indirect_ubos_use_sampler = true;
/* There is no vec4 mode on Gen10+, and we don't use it at all on Gen8+. */
for (int i = MESA_SHADER_VERTEX; i < MESA_ALL_SHADER_STAGES; i++) {
compiler->scalar_stage[i] = devinfo->gen >= 8 ||
compiler->scalar_stage[i] = devinfo->ver >= 8 ||
i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE;
}
@@ -148,14 +148,14 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
* destination type can be Quadword and source type Doubleword for Gen8 and
* Gen9. So, lower 64 bit multiply instruction on rest of the platforms.
*/
if (devinfo->gen < 8 || devinfo->gen > 9)
if (devinfo->ver < 8 || devinfo->ver > 9)
int64_options |= nir_lower_imul_2x32_64;
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
compiler->glsl_compiler_options[i].MaxIfDepth =
devinfo->gen < 6 ? 16 : UINT_MAX;
devinfo->ver < 6 ? 16 : UINT_MAX;
/* We handle this in NIR */
compiler->glsl_compiler_options[i].EmitNoIndirectInput = false;
@@ -177,20 +177,20 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
/* Prior to Gen6, there are no three source operations, and Gen11 loses
* LRP.
*/
nir_options->lower_ffma16 = devinfo->gen < 6;
nir_options->lower_ffma32 = devinfo->gen < 6;
nir_options->lower_ffma64 = devinfo->gen < 6;
nir_options->lower_flrp32 = devinfo->gen < 6 || devinfo->gen >= 11;
nir_options->lower_fpow = devinfo->gen >= 12;
nir_options->lower_ffma16 = devinfo->ver < 6;
nir_options->lower_ffma32 = devinfo->ver < 6;
nir_options->lower_ffma64 = devinfo->ver < 6;
nir_options->lower_flrp32 = devinfo->ver < 6 || devinfo->ver >= 11;
nir_options->lower_fpow = devinfo->ver >= 12;
nir_options->lower_rotate = devinfo->gen < 11;
nir_options->lower_bitfield_reverse = devinfo->gen < 7;
nir_options->lower_rotate = devinfo->ver < 11;
nir_options->lower_bitfield_reverse = devinfo->ver < 7;
nir_options->lower_int64_options = int64_options;
nir_options->lower_doubles_options = fp64_options;
/* Starting with Gen11, we lower away 8-bit arithmetic */
nir_options->support_8bit_alu = devinfo->gen < 11;
nir_options->support_8bit_alu = devinfo->ver < 11;
nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
@@ -213,7 +213,7 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler)
{
uint64_t config = 0;
insert_u64_bit(&config, compiler->precise_trig);
if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) {
if (compiler->devinfo->ver >= 8 && compiler->devinfo->ver < 10) {
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);