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docs/isl: remove empty headings

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Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19461>
This commit is contained in:
Erik Faye-Lund
2022-11-02 14:00:31 +01:00
committed by Marge Bot
parent d2b3ebf0d8
commit ab1727237a
1 changed files with 0 additions and 6 deletions
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docs/isl/tiling.rst
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@@ -134,7 +134,6 @@ tile, the data is arranged in an X-major linear fashion. You can also look at
X-tiling as being an 8x8 cache line grid where the cache lines are arranged
X-major as follows:
===== ===== ===== ===== ===== ===== ===== =====
===== ===== ===== ===== ===== ===== ===== =====
0x000 0x040 0x080 0x0c0 0x100 0x140 0x180 0x1c0
0x200 0x240 0x280 0x2c0 0x300 0x340 0x380 0x3c0
@@ -171,7 +170,6 @@ Y-tiling
The Y-tiling format, also available since gen4, is substantially different from
X-tiling and performs much better in practice. Each Y-tile is an 8x8 grid of cache lines arranged Y-major as follows:
===== ===== ===== ===== ===== ===== ===== =====
===== ===== ===== ===== ===== ===== ===== =====
0x000 0x200 0x400 0x600 0x800 0xa00 0xc00 0xe00
0x040 0x240 0x440 0x640 0x840 0xa40 0xc40 0xe40
@@ -185,7 +183,6 @@ X-tiling and performs much better in practice. Each Y-tile is an 8x8 grid of ca
Each 64B cache line within the tile is laid out as 4 rows of 16B each:
==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ====
==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ====
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
@@ -216,7 +213,6 @@ buffers. W-tiling is similar to Y-tiling in that it's arranged as an 8x8
Y-major grid of cache lines. The bytes within each cache line are arranged as
follows:
==== ==== ==== ==== ==== ==== ==== ====
==== ==== ==== ==== ==== ==== ==== ====
0x00 0x01 0x04 0x05 0x10 0x11 0x14 0x15
0x02 0x03 0x06 0x07 0x12 0x13 0x16 0x17
@@ -253,7 +249,6 @@ The tile4 format, introduced on Xe-HP, is somewhat similar to Y but with more
internal shuffling. Each tile4 tile is an 8x8 grid of cache lines arranged
as follows:
===== ===== ===== ===== ===== ===== ===== =====
===== ===== ===== ===== ===== ===== ===== =====
0x000 0x040 0x080 0x0a0 0x200 0x240 0x280 0x2a0
0x100 0x140 0x180 0x1a0 0x300 0x340 0x380 0x3a0
@@ -268,7 +263,6 @@ as follows:
Each 64B cache line within the tile is laid out the same way as for a Y-tile,
as 4 rows of 16B each:
==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ====
==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ====
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f