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radeonsi: add support for Renoir

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Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák
2019-01-02 15:50:13 -05:00
parent a3d6024199
commit aafc95ceb6
8 changed files with 17 additions and 2 deletions
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2
include/pci_ids/radeonsi_pci_ids.h
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@@ -254,6 +254,8 @@ CHIPSET(0x66AF, VEGA20)
CHIPSET(0x15DD, RAVEN)
CHIPSET(0x15D8, RAVEN)
CHIPSET(0x1636, RENOIR)
CHIPSET(0x738C, ARCTURUS)
CHIPSET(0x7388, ARCTURUS)
CHIPSET(0x738E, ARCTURUS)

2
src/amd/addrlib/src/amdgpu_asic_addr.h
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@@ -93,6 +93,7 @@
#define AMDGPU_RAVEN_RANGE 0x01, 0x81
#define AMDGPU_RAVEN2_RANGE 0x81, 0xFF
#define AMDGPU_RENOIR_RANGE 0x01, 0x91
#define AMDGPU_ARCTURUS_RANGE 0x32, 0xFF
@@ -141,6 +142,7 @@
#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
#define ASICREV_IS_RENOIR(r) ASICREV_IS(r, RENOIR)
#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)

5
src/amd/addrlib/src/gfx9/gfx9addrlib.cpp
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@@ -1312,6 +1312,11 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
m_settings.applyAliasFix = 1;
}
if (ASICREV_IS_RENOIR(uChipRevision))
{
m_settings.isRaven = 1;
}
m_settings.isDcn1 = m_settings.isRaven;
m_settings.metaBaseAlignFix = 1;

3
src/amd/common/ac_gpu_info.c
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@@ -478,7 +478,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
if (info->drm_minor >= 31 &&
(info->family == CHIP_RAVEN ||
info->family == CHIP_RAVEN2)) {
info->family == CHIP_RAVEN2 ||
info->family == CHIP_RENOIR)) {
if (info->num_render_backends == 1)
info->use_display_dcc_unaligned = true;
else

1
src/amd/common/ac_llvm_util.c
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@@ -132,6 +132,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
case CHIP_VEGA20:
return "gfx906";
case CHIP_RAVEN2:
case CHIP_RENOIR:
return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
case CHIP_ARCTURUS:
return "gfx908";

1
src/amd/common/amd_family.h
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@@ -97,6 +97,7 @@ enum radeon_family {
CHIP_VEGA20,
CHIP_RAVEN,
CHIP_RAVEN2,
CHIP_RENOIR,
CHIP_ARCTURUS,
CHIP_NAVI10,
CHIP_NAVI12,

4
src/gallium/drivers/radeonsi/si_pipe.c
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@@ -1150,6 +1150,7 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
sscreen->info.family == CHIP_RAVEN;
sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
sscreen->info.family == CHIP_RENOIR ||
sscreen->info.chip_class >= GFX10;
sscreen->use_ngg = sscreen->info.chip_class >= GFX10;
sscreen->use_ngg_streamout = sscreen->info.chip_class >= GFX10;
@@ -1195,7 +1196,8 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
(sscreen->info.family == CHIP_STONEY ||
sscreen->info.family == CHIP_VEGA12 ||
sscreen->info.family == CHIP_RAVEN ||
sscreen->info.family == CHIP_RAVEN2);
sscreen->info.family == CHIP_RAVEN2 ||
sscreen->info.family == CHIP_RENOIR);
}
sscreen->dcc_msaa_allowed =

1
src/gallium/drivers/radeonsi/si_state.c
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@@ -5685,6 +5685,7 @@ static void si_init_config(struct si_context *sctx)
break;
case CHIP_RAVEN:
case CHIP_RAVEN2:
case CHIP_RENOIR:
case CHIP_NAVI10:
case CHIP_NAVI12:
pc_lines = 1024;