iris: Remove depth cache set tracking and synchronization.
The depth cache set is now redundant with the more general seqno matrix-based cache tracking mechanism. Removed as a separate patch for bisectability. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
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@@ -203,8 +203,6 @@ iris_init_batch(struct iris_context *ice,
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batch->cache.render = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
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_mesa_key_pointer_equal);
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batch->cache.depth = _mesa_set_create(NULL, _mesa_hash_pointer,
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_mesa_key_pointer_equal);
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memset(batch->other_batches, 0, sizeof(batch->other_batches));
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@@ -446,7 +444,6 @@ iris_batch_free(struct iris_batch *batch)
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iris_destroy_hw_context(bufmgr, batch->hw_ctx_id);
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_mesa_hash_table_destroy(batch->cache.render, NULL);
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_mesa_set_destroy(batch->cache.depth, NULL);
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if (unlikely(INTEL_DEBUG))
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gen_batch_decode_ctx_finish(&batch->decoder);
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@@ -132,13 +132,6 @@ struct iris_batch {
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* cache domain that isn't coherent with it (i.e. the sampler).
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*/
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struct hash_table *render;
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/**
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* Set of struct brw_bo * that have been used as a depth buffer within
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* this batchbuffer and would need flushing before being used from
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* another cache domain that isn't coherent with it (i.e. the sampler).
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*/
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struct set *depth;
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} cache;
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struct gen_batch_decode_ctx decoder;
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@@ -372,10 +372,6 @@ iris_blorp_exec(struct blorp_batch *blorp_batch,
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params->dst.view.format,
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params->dst.aux_usage);
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}
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if (params->depth.enabled)
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iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
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if (params->stencil.enabled)
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iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
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if (params->src.enabled)
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iris_bo_bump_seqno(params->src.addr.buffer, batch->next_seqno,
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@@ -922,7 +922,6 @@ void iris_render_cache_add_bo(struct iris_batch *batch,
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enum isl_format format,
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enum isl_aux_usage aux_usage);
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void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
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void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
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int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
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struct pipe_driver_query_info *info);
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int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
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@@ -307,8 +307,7 @@ iris_texture_barrier(struct pipe_context *ctx, unsigned flags)
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struct iris_batch *compute_batch = &ice->batches[IRIS_BATCH_COMPUTE];
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if (render_batch->contains_draw ||
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render_batch->cache.render->entries ||
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render_batch->cache.depth->entries) {
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render_batch->cache.render->entries) {
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iris_batch_maybe_flush(render_batch, 48);
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iris_emit_pipe_control_flush(render_batch,
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"API: texture barrier (1/2)",
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@@ -296,9 +296,6 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice,
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zs_surf->u.tex.first_layer, num_layers,
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ice->state.depth_writes_enabled);
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}
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if (ice->state.depth_writes_enabled)
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iris_depth_cache_add_bo(batch, z_res->bo);
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}
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if (s_res) {
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@@ -307,9 +304,6 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice,
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zs_surf->u.tex.first_layer, num_layers,
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s_res->aux.usage);
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}
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if (ice->state.stencil_writes_enabled)
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iris_depth_cache_add_bo(batch, s_res->bo);
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}
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}
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@@ -347,9 +341,6 @@ iris_cache_sets_clear(struct iris_batch *batch)
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{
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hash_table_foreach(batch->cache.render, render_entry)
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_mesa_hash_table_remove(batch->cache.render, render_entry);
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set_foreach(batch->cache.depth, depth_entry)
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_mesa_set_remove(batch->cache.depth, depth_entry);
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}
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/**
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@@ -385,8 +376,7 @@ void
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iris_cache_flush_for_read(struct iris_batch *batch,
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struct iris_bo *bo)
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{
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if (_mesa_hash_table_search_pre_hashed(batch->cache.render, bo->hash, bo) ||
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_mesa_set_search_pre_hashed(batch->cache.depth, bo->hash, bo))
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if (_mesa_hash_table_search_pre_hashed(batch->cache.render, bo->hash, bo))
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iris_flush_depth_and_render_caches(batch);
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iris_emit_buffer_barrier_for(batch, bo, IRIS_DOMAIN_OTHER_READ);
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@@ -406,9 +396,6 @@ iris_cache_flush_for_render(struct iris_batch *batch,
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{
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iris_emit_buffer_barrier_for(batch, bo, IRIS_DOMAIN_RENDER_WRITE);
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if (_mesa_set_search_pre_hashed(batch->cache.depth, bo->hash, bo))
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iris_flush_depth_and_render_caches(batch);
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/* Check to see if this bo has been used by a previous rendering operation
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* but with a different format or aux usage. If it has, flush the render
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* cache so we ensure that it's only in there with one format or aux usage
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@@ -469,12 +456,6 @@ iris_cache_flush_for_depth(struct iris_batch *batch,
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iris_emit_buffer_barrier_for(batch, bo, IRIS_DOMAIN_DEPTH_WRITE);
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}
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void
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iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo)
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{
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_mesa_set_add_pre_hashed(batch->cache.depth, bo->hash, bo);
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}
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static void
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iris_resolve_color(struct iris_context *ice,
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struct iris_batch *batch,
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