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ac/nir: use store_buffer_amd's base index

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This allows ACO to combine the addition into the store without checking
for wraparound.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20296>
This commit is contained in:
Rhys Perry
2022-12-13 15:08:58 +00:00
committed by Marge Bot
parent 39c214769b
commit aa6b2ec46a
1 changed files with 3 additions and 3 deletions
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6
src/amd/common/ac_nir.c
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@@ -620,15 +620,14 @@ lower_legacy_gs_emit_vertex_with_counter(nir_builder *b, nir_intrinsic_instr *in
((s->info->streams[i] >> (j * 2)) & 0x3) != stream) ((s->info->streams[i] >> (j * 2)) & 0x3) != stream)
continue; continue;
unsigned base = offset * b->shader->info.gs.vertices_out; unsigned base = offset * b->shader->info.gs.vertices_out * 4;
offset++; offset++;
/* no one set this output, skip the buffer store */ /* no one set this output, skip the buffer store */
if (!output) if (!output)
continue; continue;
nir_ssa_def *voffset = nir_iadd_imm(b, vtxidx, base); nir_ssa_def *voffset = nir_ishl_imm(b, vtxidx, 2);
voffset = nir_ishl_imm(b, voffset, 2);
/* extend 8/16 bit to 32 bit, 64 bit has been lowered */ /* extend 8/16 bit to 32 bit, 64 bit has been lowered */
nir_ssa_def *data = nir_u2uN(b, output, 32); nir_ssa_def *data = nir_u2uN(b, output, 32);
@@ -636,6 +635,7 @@ lower_legacy_gs_emit_vertex_with_counter(nir_builder *b, nir_intrinsic_instr *in
nir_store_buffer_amd(b, data, gsvs_ring, voffset, soffset, nir_imm_int(b, 0), nir_store_buffer_amd(b, data, gsvs_ring, voffset, soffset, nir_imm_int(b, 0),
.access = ACCESS_COHERENT | ACCESS_STREAM_CACHE_POLICY | .access = ACCESS_COHERENT | ACCESS_STREAM_CACHE_POLICY |
ACCESS_IS_SWIZZLED_AMD, ACCESS_IS_SWIZZLED_AMD,
.base = base,
/* For ACO to not reorder this store around EmitVertex/EndPrimitve */ /* For ACO to not reorder this store around EmitVertex/EndPrimitve */
.memory_modes = nir_var_shader_out); .memory_modes = nir_var_shader_out);
} }