From a95d7e46b61e094911d4e6baa9f75af3f218f516 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 4 Jun 2024 09:07:02 +0200 Subject: [PATCH] radv: update VGT_TESS_DISTRIBUTION.ACCUM_ISOLINE value Based on PAL/RadeonSI. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_queue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 96c6edb4301..574b38c5170 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -1106,7 +1106,7 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) S_028B50_DONUT_SPLIT_GFX9(24) | S_028B50_TRAP_SPLIT(6)); } else if (pdev->info.gfx_level >= GFX9) { radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, - S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) | + S_028B50_ACCUM_ISOLINE(12) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) | S_028B50_DONUT_SPLIT_GFX9(24) | S_028B50_TRAP_SPLIT(6)); } else if (pdev->info.gfx_level >= GFX8) { uint32_t vgt_tess_distribution;